diff -Naur linux.225/Makefile linux.225.visws/Makefile --- linux.225/Makefile Tue Mar 23 14:48:17 1999 +++ linux.225.visws/Makefile Thu Apr 15 17:51:21 1999 @@ -18,7 +18,7 @@ HOSTCC =gcc HOSTCFLAGS =-Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -CROSS_COMPILE = +CROSS_COMPILE = AS =$(CROSS_COMPILE)as LD =$(CROSS_COMPILE)ld @@ -93,6 +93,11 @@ AFLAGS += -D__SMP__ endif +ifdef CONFIG_VISWS +CFLAGS += -DCONFIG_VISWS_HACKS +AFLAGS += -DCONFIG_VISWS_HACKS +endif + # # if you want the RAM disk device, define this to be the # size in blocks. @@ -130,6 +135,10 @@ DRIVERS := $(DRIVERS) drivers/cdrom/cdrom.a endif +ifeq ($(CONFIG_USB),y) +DRIVERS := $(DRIVERS) drivers/uusbd/usb.a +endif + ifeq ($(CONFIG_SOUND),y) DRIVERS := $(DRIVERS) drivers/sound/sound.a endif @@ -320,6 +329,7 @@ if [ -f HAM_MODULES ]; then inst_mod HAM_MODULES net; fi; \ if [ -f SOUND_MODULES ]; then inst_mod SOUND_MODULES sound; fi; \ if [ -f VIDEO_MODULES ]; then inst_mod VIDEO_MODULES video; fi; \ + if [ -f UUSBD_MODULES ]; then inst_mod UUSBD_MODULES uusbd; fi; \ if [ -f FC4_MODULES ]; then inst_mod FC4_MODULES fc4; fi; \ if [ -f IRDA_MODULES ]; then inst_mod IRDA_MODULES net; fi; \ \ diff -Naur linux.225/arch/i386/kernel/bios32.c linux.225.visws/arch/i386/kernel/bios32.c --- linux.225/arch/i386/kernel/bios32.c Sun Mar 21 07:24:54 1999 +++ linux.225.visws/arch/i386/kernel/bios32.c Thu Apr 15 17:43:05 1999 @@ -352,6 +352,7 @@ * * This should be close to trivial, but it isn't, because there are buggy * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. + * XXX maybe Lithium is "buggy" this way as well? */ __initfunc(int pci_sanity_check(struct pci_access *a)) { @@ -1143,7 +1144,12 @@ pci_write_config_word(dev, PCI_COMMAND, cmd); } } -#if defined(CONFIG_X86_IO_APIC) +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_X86_VISWS_APIC) +#ifdef CONFIG_X86_IO_APIC +#define PCI_IRQ(b,s,p) IO_APIC_get_PCI_irq_vector(b,s,p) +#elif CONFIG_X86_VISWS_APIC +#define PCI_IRQ(b,s,p) visws_get_PCI_irq_vector(b,s,p) +#endif /* * Recalculate IRQ numbers if we use the I/O APIC */ @@ -1154,13 +1160,14 @@ pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); if (pin) { pin--; /* interrupt pins are numbered starting from 1 */ - irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); + irq = PCI_IRQ(dev->bus->number, + PCI_SLOT(dev->devfn), pin); if (irq < 0 && dev->bus->parent) { /* go back to the bridge */ struct pci_dev * bridge = dev->bus->self; pin = (pin + PCI_SLOT(dev->devfn)) % 4; - irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, - PCI_SLOT(bridge->devfn), pin); + irq = PCI_IRQ(bridge->bus->number, + PCI_SLOT(bridge->devfn), pin); if (irq >= 0) printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n", bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq); diff -Naur linux.225/arch/i386/kernel/head.S linux.225.visws/arch/i386/kernel/head.S --- linux.225/arch/i386/kernel/head.S Thu Jan 14 22:57:25 1999 +++ linux.225.visws/arch/i386/kernel/head.S Thu Apr 15 17:43:05 1999 @@ -40,6 +40,12 @@ ENTRY(stext) ENTRY(_stext) startup_32: +#ifdef CONFIG_VISWS_HACKS + movl $0x101000,%eax + movl %eax,%cr3 + lgdt gdt_descr + lidt idt_descr +#endif /* * Set segments to known values */ diff -Naur linux.225/arch/i386/kernel/io_apic.c linux.225.visws/arch/i386/kernel/io_apic.c --- linux.225/arch/i386/kernel/io_apic.c Tue Feb 16 14:20:05 1999 +++ linux.225.visws/arch/i386/kernel/io_apic.c Thu Apr 15 17:43:05 1999 @@ -555,27 +555,6 @@ return 0; } -int irq_vector[NR_IRQS] = { IRQ0_TRAP_VECTOR , 0 }; - -static int __init assign_irq_vector(int irq) -{ - static int current_vector = IRQ0_TRAP_VECTOR, offset = 0; - if (IO_APIC_VECTOR(irq) > 0) - return IO_APIC_VECTOR(irq); - current_vector += 8; - if (current_vector > 0xFE) { - offset++; - current_vector = IRQ0_TRAP_VECTOR + offset; - printk("WARNING: ASSIGN_IRQ_VECTOR wrapped back to %02X\n", - current_vector); - } - if (current_vector == SYSCALL_VECTOR) - panic("ran out of interrupt sources!"); - - IO_APIC_VECTOR(irq) = current_vector; - return current_vector; -} - void __init setup_IO_APIC_irqs(void) { struct IO_APIC_route_entry entry; @@ -1186,7 +1165,7 @@ if (IO_APIC_IRQ(i)) irq_desc[i].handler = &no_irq_type; } - init_IRQ_SMP(); + init_IRQ_MORE_TRAPS(); } /* diff -Naur linux.225/arch/i386/kernel/irq.c linux.225.visws/arch/i386/kernel/irq.c --- linux.225/arch/i386/kernel/irq.c Tue Feb 16 14:20:05 1999 +++ linux.225.visws/arch/i386/kernel/irq.c Thu Apr 15 17:43:05 1999 @@ -293,7 +293,7 @@ */ BUILD_16_IRQS(0x0) -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_X86_VISWS_APIC) /* * The IO-APIC gives us many more interrupt sources. Most of these * are unused but an SMP system is supposed to have enough memory ... @@ -349,7 +349,7 @@ static void (*interrupt[NR_IRQS])(void) = { IRQLIST_16(0x0), -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_X86_VISWS_APIC) IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), @@ -1018,6 +1018,30 @@ return irq_found; } +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_X86_VISWS_APIC) + +int irq_vector[NR_IRQS] = { IRQ0_TRAP_VECTOR , 0 }; + +int __init assign_irq_vector(int irq) +{ + static int current_vector = IRQ0_TRAP_VECTOR, offset = 0; + if (IRQ_VECTOR(irq) > 0) + return IRQ_VECTOR(irq); + current_vector += 8; + if (current_vector > 0xFE) { + offset++; + current_vector = IRQ0_TRAP_VECTOR + offset; + printk("WARNING: ASSIGN_IRQ_VECTOR wrapped back to %02X\n", + current_vector); + } + if (current_vector == SYSCALL_VECTOR) + panic("ran out of interrupt sources!"); + + IRQ_VECTOR(irq) = current_vector; + return current_vector; +} +#endif + void init_ISA_irqs (void) { int i; @@ -1045,11 +1069,6 @@ { int i; -#ifndef CONFIG_X86_VISWS_APIC - init_ISA_irqs(); -#else - init_VISWS_APIC_irqs(); -#endif /* * Cover the whole vector space, no vector can escape * us. (some of these will be overridden and become @@ -1061,11 +1080,17 @@ set_intr_gate(vector, interrupt[i]); } +#ifndef CONFIG_X86_VISWS_APIC + init_ISA_irqs(); +#else + init_VISWS_APIC_irqs(); +#endif + #ifdef __SMP__ /* IRQ0 must be given a fixed assignment and initialized - before init_IRQ_SMP. + before init_IRQ_MORE_TRAPS. */ set_intr_gate(IRQ0_TRAP_VECTOR, interrupt[0]); @@ -1107,13 +1132,16 @@ #endif } -#ifdef CONFIG_X86_IO_APIC -__initfunc(void init_IRQ_SMP(void)) +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_X86_VISWS_APIC) +/* + * An IO-APIC PC has more traps if SMP. + * The Visual Workstation always has more traps (whether SMP or not). + */ +__initfunc(void init_IRQ_MORE_TRAPS(void)) { int i; for (i = 0; i < NR_IRQS ; i++) - if (IO_APIC_VECTOR(i) > 0) - set_intr_gate(IO_APIC_VECTOR(i), interrupt[i]); + if (IRQ_VECTOR(i) > 0) + set_intr_gate(IRQ_VECTOR(i), interrupt[i]); } #endif - diff -Naur linux.225/arch/i386/kernel/irq.h linux.225.visws/arch/i386/kernel/irq.h --- linux.225/arch/i386/kernel/irq.h Sun Mar 28 10:04:44 1999 +++ linux.225.visws/arch/i386/kernel/irq.h Fri Apr 16 17:11:57 1999 @@ -78,9 +78,10 @@ extern irq_desc_t irq_desc[NR_IRQS]; extern int irq_vector[NR_IRQS]; -#define IO_APIC_VECTOR(irq) irq_vector[irq] +#define IRQ_VECTOR(irq) irq_vector[irq] -extern void init_IRQ_SMP(void); +extern int assign_irq_vector(int irq); +extern void init_IRQ_MORE_TRAPS(void); extern int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); extern int setup_x86_irq(unsigned int, struct irqaction *); @@ -102,6 +103,7 @@ extern void init_VISWS_APIC_irqs(void); extern void setup_IO_APIC(void); extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn); +extern int visws_get_PCI_irq_vector(int bus, int slot, int fn); extern void make_8259A_irq(unsigned int irq); extern void send_IPI(int dest, int vector); extern void init_pic_mode(void); diff -Naur linux.225/arch/i386/kernel/process.c linux.225.visws/arch/i386/kernel/process.c --- linux.225/arch/i386/kernel/process.c Wed Mar 10 16:52:44 1999 +++ linux.225.visws/arch/i386/kernel/process.c Fri Apr 16 14:08:16 1999 @@ -164,6 +164,61 @@ return 0; } +#ifdef CONFIG_VISWS + +#include +#include + +static void +visws_restart(void) +{ + printk("visws restart\n"); + + /* + * This machine resets by poking this + * register on PIIX4. + */ + outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT); +} + +static void +visws_power_off(void) +{ + unsigned short pm_status; + + printk("visws power off\n"); + + /* + * Clearing the event before the button is released seems to + * re-enable it, thus preventing shutdown. + */ + while ((pm_status = inw(PMSTS_PORT)) & 0x100) { + outw(pm_status, PMSTS_PORT); + } + + /* + * Here's the magic write that actually sequences + * the PIIX4 to shutdown the power. + */ + outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT); + + /* + * Need 10msec delay before generating special + * cycle so PIIX4 will shut down system. + */ + udelay(10000); + + /* + * PIIX4 has asserted stopclk and is waiting to see + * the stop special cycle. Generate one of those + * by hand now. + */ + pcibios_write_config_dword(PIIX4_BUS, SPECIAL_DEV, SPECIAL_REG, + PIIX_SPECIAL_STOP); +} +#endif /* CONFIG_VISWS */ + + /* * This routine reboots the machine by asking the keyboard * controller to pulse the reset-line low. We try that for a while, @@ -275,6 +330,10 @@ init_pic_mode(); #endif +#ifdef CONFIG_VISWS + visws_restart(); +#endif /* CONFIG_VISWS */ + if(!reboot_thru_bios) { /* rebooting needs to touch the page at absolute addr 0 */ *((unsigned short *)__va(0x472)) = reboot_mode; @@ -382,6 +441,9 @@ void machine_power_off(void) { +#ifdef CONFIG_VISWS + visws_power_off(); +#endif /* CONFIG_VISWS */ #if defined(CONFIG_APM) && defined(CONFIG_APM_POWER_OFF) apm_power_off(); #endif diff -Naur linux.225/arch/i386/kernel/setup.c linux.225.visws/arch/i386/kernel/setup.c --- linux.225/arch/i386/kernel/setup.c Mon Mar 22 11:18:17 1999 +++ linux.225.visws/arch/i386/kernel/setup.c Tue Apr 20 15:35:16 1999 @@ -38,7 +38,10 @@ #include #include #include -#include +#ifdef CONFIG_VISWS +#include +#include +#endif /* * Machine setup.. @@ -112,54 +115,12 @@ char visws_board_type = -1; char visws_board_rev = -1; -#define PIIX_PM_START 0x0F80 - -#define SIO_GPIO_START 0x0FC0 - -#define SIO_PM_START 0x0FC8 - -#define PMBASE PIIX_PM_START -#define GPIREG0 (PMBASE+0x30) -#define GPIREG(x) (GPIREG0+((x)/8)) -#define PIIX_GPI_BD_ID1 18 -#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1) - -#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8) - -#define SIO_INDEX 0x2e -#define SIO_DATA 0x2f - -#define SIO_DEV_SEL 0x7 -#define SIO_DEV_ENB 0x30 -#define SIO_DEV_MSB 0x60 -#define SIO_DEV_LSB 0x61 - -#define SIO_GP_DEV 0x7 - -#define SIO_GP_BASE SIO_GPIO_START -#define SIO_GP_MSB (SIO_GP_BASE>>8) -#define SIO_GP_LSB (SIO_GP_BASE&0xff) - -#define SIO_GP_DATA1 (SIO_GP_BASE+0) - -#define SIO_PM_DEV 0x8 - -#define SIO_PM_BASE SIO_PM_START -#define SIO_PM_MSB (SIO_PM_BASE>>8) -#define SIO_PM_LSB (SIO_PM_BASE&0xff) -#define SIO_PM_INDEX (SIO_PM_BASE+0) -#define SIO_PM_DATA (SIO_PM_BASE+1) - -#define SIO_PM_FER2 0x1 - -#define SIO_PM_GP_EN 0x80 - static void visws_get_board_type_and_rev(void) { int raw; - visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG) + visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_MASK) >> PIIX_GPI_BD_SHIFT; /* * Get Board rev. @@ -211,29 +172,38 @@ raw = inb_p(SIO_GP_DATA1); raw &= 0x7f; /* 7 bits of valid board revision ID. */ - if (visws_board_type == VISWS_320) { + switch (visws_board_type) { + case VISWS_320: if (raw < 0x6) { visws_board_rev = 4; } else if (raw < 0xc) { visws_board_rev = 5; } else { visws_board_rev = 6; - - } - } else if (visws_board_type == VISWS_540) { - visws_board_rev = 2; - } else { - visws_board_rev = raw; } - - printk("Silicon Graphics %s (rev %d)\n", - visws_board_type == VISWS_320 ? "320" : - (visws_board_type == VISWS_540 ? "540" : - "unknown"), - visws_board_rev); + break; + case VISWS_540: + visws_board_rev = 2; + break; + default: + visws_board_rev = raw; + break; } + + printk("Silicon Graphics %s (rev %d)\n", + visws_board_type == VISWS_320 ? "320" : + (visws_board_type == VISWS_540 ? "540" : + "unknown"), + visws_board_rev); +} #endif +#ifdef CONFIG_VISWS_HACKS +#ifdef CONFIG_FB_SGIVW +extern u_long sgivwfb_mem_phys; +extern u_long sgivwfb_mem_size; +#endif +#endif static char command_line[COMMAND_LINE_SIZE] = { 0, }; char saved_command_line[COMMAND_LINE_SIZE]; @@ -278,6 +248,30 @@ #endif memory_end &= PAGE_MASK; + +#ifdef CONFIG_VISWS_HACKS + +#define MEGS 128 /* XXX HACK how to get mem config? */ + /* XXX 128 will always work... smallest mem size */ + +printk("VISWS HACK: hard-wiring physical mem size to %dMb\n", MEGS); +memory_end = MEGS<<20; + +#ifdef CONFIG_FB_SGIVW + +#define VISWS_VID_MEGS 16 +printk("VISWS HACK: taking %dMb for frame buffer -- leaving %dMb for kernel\n", +VISWS_VID_MEGS, MEGS-VISWS_VID_MEGS); +memory_end = (MEGS-VISWS_VID_MEGS)<<20; +sgivwfb_mem_phys = memory_end; +sgivwfb_mem_size = VISWS_VID_MEGS<<20; + +printk("sgivwfb_mem_phys %x\n", sgivwfb_mem_phys); + +#endif +#endif + + #ifdef CONFIG_BLK_DEV_RAM rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK; rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0); @@ -369,12 +363,13 @@ request_region(0xf0,0x10,"fpu"); #ifdef CONFIG_VT -#if defined(CONFIG_VGA_CONSOLE) +#if defined(CONFIG_VGA_CONSOLE) && !defined(CONFIG_VISWS) conswitchp = &vga_con; #elif defined(CONFIG_DUMMY_CONSOLE) conswitchp = &dummy_con; #endif #endif + /* * Check the bugs that will bite us before we get booting */ diff -Naur linux.225/arch/i386/kernel/time.c linux.225.visws/arch/i386/kernel/time.c --- linux.225/arch/i386/kernel/time.c Thu Mar 11 23:25:05 1999 +++ linux.225.visws/arch/i386/kernel/time.c Fri Apr 16 12:59:17 1999 @@ -53,7 +53,7 @@ #include #include -#include +#include /* * for x86_do_profile() @@ -678,9 +678,6 @@ /* Enable (unmask) the timer interrupt */ co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); - /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */ - setup_x86_irq(CO_IRQ_TIMER, &irq0); -#else - setup_x86_irq(0, &irq0); #endif + setup_x86_irq(0, &irq0); } diff -Naur linux.225/arch/i386/kernel/trampoline.S linux.225.visws/arch/i386/kernel/trampoline.S --- linux.225/arch/i386/kernel/trampoline.S Wed May 6 11:42:54 1998 +++ linux.225.visws/arch/i386/kernel/trampoline.S Thu Apr 15 17:43:05 1999 @@ -54,8 +54,13 @@ lmsw %ax # into protected mode jmp flush_instr flush_instr: +#ifdef CONFIG_VISWS_HACKS + ljmpl $__KERNEL_CS, $0x00100016 + # jump to startup_32 + 0x16 +#else ljmpl $__KERNEL_CS, $0x00100000 # jump to startup_32 +#endif idt_48: .word 0 # idt limit = 0 diff -Naur linux.225/arch/i386/kernel/traps.c linux.225.visws/arch/i386/kernel/traps.c --- linux.225/arch/i386/kernel/traps.c Tue Feb 16 14:20:05 1999 +++ linux.225.visws/arch/i386/kernel/traps.c Fri Apr 16 12:59:24 1999 @@ -38,8 +38,8 @@ #ifdef CONFIG_X86_VISWS_APIC #include -#include -#include +#include +#include #endif #include "irq.h" @@ -640,9 +640,14 @@ printk("Lithium PCI Bridge B (PIIX4), Bus Number: %d\n", li_pcib_read16(LI_PCI_BUSNUM) & 0xff); - /* XXX blindly enables all interrupts */ - li_pcia_write16(LI_PCI_INTEN, 0xffff); - li_pcib_write16(LI_PCI_INTEN, 0xffff); + /* XXX blindly enables all device interrupts */ + /* XXX even more blindly does not enable any error interrupts */ + /* NOTE: Lithium error interrupts share LI_INTD */ +#define A01234 (LI_INTA_0|LI_INTA_1|LI_INTA_2|LI_INTA_3|LI_INTA_4) +#define BCD (LI_INTB|LI_INTC|LI_INTD) +#define ALLDEVS (A01234|BCD) + li_pcia_write16(LI_PCI_INTEN, ALLDEVS); + li_pcib_write16(LI_PCI_INTEN, ALLDEVS); } static void diff -Naur linux.225/arch/i386/kernel/visws_apic.c linux.225.visws/arch/i386/kernel/visws_apic.c --- linux.225/arch/i386/kernel/visws_apic.c Wed Jan 20 10:18:53 1999 +++ linux.225.visws/arch/i386/kernel/visws_apic.c Fri Apr 16 12:59:27 1999 @@ -36,7 +36,7 @@ #include #include -#include +#include #include "irq.h" @@ -51,8 +51,6 @@ * controller. Device drivers only see the virtual interrupt sources. */ -#define CO_IRQ_BASE 0x20 /* This is the 0x20 in init_IRQ()! */ - static void startup_piix4_master_irq(unsigned int irq); static void shutdown_piix4_master_irq(unsigned int irq); static void do_piix4_master_IRQ(unsigned int irq, struct pt_regs * regs); @@ -132,12 +130,12 @@ * Set the given Cobalt APIC Redirection Table entry to point * to the given IDT vector/index. */ -static void co_apic_set(int entry, int idtvec) +static void co_apic_set(int entry, int irq) { - co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (CO_IRQ_BASE+idtvec)); + printk("IRQ %d, Cobalt APIC Entry %d, IDT Vector %x\n", + irq, entry, IRQ_VECTOR(irq)); + co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL|IRQ_VECTOR(irq)); co_apic_write(CO_APIC_HI(entry), 0); - - printk("Cobalt APIC Entry %d IDT Vector %d\n", entry, idtvec); } /* @@ -148,21 +146,32 @@ static void startup_cobalt_irq(unsigned int irq) { /* - * These "irq"'s are wired to the same Cobalt APIC entries - * for all (known) motherboard types/revs + * Protect this code from probe_irq_on/off() */ - switch (irq) { - case CO_IRQ_TIMER: co_apic_set(CO_APIC_CPU, CO_IRQ_TIMER); - return; - - case CO_IRQ_ENET: co_apic_set(CO_APIC_ENET, CO_IRQ_ENET); - return; + if (irq_desc[irq].status & IRQ_AUTODETECT) { + return; + } - case CO_IRQ_SERIAL: return; /* XXX move to piix4-8259 "virtual" */ + /* + * These irqs go to Cobalt directly + */ + if (IS_CO_APIC(irq)) { + co_apic_set(CO_APIC(irq), irq); + return; + } - case CO_IRQ_8259: co_apic_set(CO_APIC_8259, CO_IRQ_8259); + /* + * Some special irqs. + */ + switch (irq) { + case 0: co_apic_set(CO_APIC_CPU, 0); return; + case 4: return; /* serial hack HACK! */ + + /* + * We use the path direct to Cobalt + */ case CO_IRQ_IDE: switch (visws_board_type) { case VISWS_320: @@ -184,8 +193,6 @@ } } break; - default: - panic("huh?"); } } @@ -200,7 +207,6 @@ spin_lock(&irq_controller_lock); { unsigned int status; - /* XXX APIC EOI? */ status = desc->status & ~IRQ_REPLAY; action = NULL; if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -322,6 +328,7 @@ * handle this 'virtual interrupt' as a Cobalt one now. */ kstat.irqs[smp_processor_id()][irq]++; + kstat.irqs[smp_processor_id()][realirq]++; do_cobalt_IRQ(realirq, regs); spin_lock(&irq_controller_lock); @@ -365,43 +372,71 @@ outb(mask, 0x21); } +/* + * Called from bios32.c:pcibios_fixup_devices() + * Our chance to fill in the proper irqs. + */ +int +visws_get_PCI_irq_vector(int bus, int slot, int line) +{ + int pin = line + 1; /* convert (MPS) "line" to (PCI) "pin" */ +printk("PCI_IRQ bus %d, slot %d, pin %d\n", bus, slot, pin); + + if (bus == 1 && slot == 3 && pin == 1) { + return CO_IRQ(CO_APIC_INTEL_ENET); + } + if (bus == 0 && slot == 4 && pin == 4) { + return CO_IRQ(CO_APIC_PIIX4_USB); + } + return 0; +} + +/* + * Maps the combination of PIIX4 8259-pair irqs plus Cobalt APIC irqs + * to CPU IDT vectors. Just initializes visws_irq_vector[] and IRQ_VEC(irq). + */ +#if (CO_IRQ_APIC0 + CO_APIC_LAST + 1) > NR_IRQS +_NR_IRQS too small +#endif + static struct irqaction master_action = { no_action, 0, 0, "PIIX4-8259", NULL, NULL }; -void init_VISWS_APIC_irqs(void) +void init_VISWS_APIC_irqs(void) /* init_IRQ() */ { int i; - for (i = 0; i < 16; i++) { + for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = 0; irq_desc[i].depth = 0; - /* - * Cobalt IRQs are mapped to standard ISA - * interrupt vectors: - */ - switch (i) { - /* - * Only CO_IRQ_8259 will be raised - * externally. - */ - case CO_IRQ_8259: + /* Some legacy irqs are handled specially */ + if (i == 0) { /* IRQ 0 is system clock -- Cobalt timer */ + irq_desc[i].handler = &cobalt_irq_type; + } else if (i == 4) { /* serial hack! */ + irq_desc[i].handler = &cobalt_irq_type; + } else if (i == CO_IRQ_IDE) { + irq_desc[i].handler = &cobalt_irq_type; + } else if (i == CO_IRQ_8259) { irq_desc[i].handler = &piix4_master_irq_type; - break; - case CO_IRQ_FLOPPY: - case CO_IRQ_PARLL: + } else if (i < 16) { /* " < 16" is magic for "is legacy" */ irq_desc[i].handler = &piix4_virtual_irq_type; - break; - default: + } else if (i <= CO_IRQ_APIC0 + CO_APIC_LAST) { irq_desc[i].handler = &cobalt_irq_type; - break; } + (void)assign_irq_vector(i); } /* * The master interrupt is always present: */ setup_x86_irq(CO_IRQ_8259, &master_action); -} + /* + * Enable IDT vectors for all valid IRQs. + * All unused IDT vectors generate 'Unexpected interrupt', + * see irq.c:strange_interrupt(). + */ + init_IRQ_MORE_TRAPS(); +} diff -Naur linux.225/drivers/block/floppy.c linux.225.visws/drivers/block/floppy.c --- linux.225/drivers/block/floppy.c Fri Mar 26 13:29:14 1999 +++ linux.225.visws/drivers/block/floppy.c Thu Apr 15 17:43:05 1999 @@ -3591,11 +3591,21 @@ /* read drive info out of physical CMOS */ drive=0; +#ifdef CONFIG_VISWS_HACKS +printk("VISWS HACK: floppy drive 0 hardwired to 1.44Mb (cmos WAR)\n"); + UDP->cmos = 4; /* drivers/block/README.fd */ +#else if (!UDP->cmos) UDP->cmos = FLOPPY0_TYPE; +#endif drive=1; +#ifdef CONFIG_VISWS_HACKS +printk("VISWS HACK: floppy drive 1 hardwired to (none) (cmos WAR)\n"); + UDP->cmos = 16; /* means "no drive" */ +#else if (!UDP->cmos && FLOPPY1_TYPE) UDP->cmos = FLOPPY1_TYPE; +#endif /* XXX */ /* additional physical CMOS drive detection should go here */ diff -Naur linux.225/drivers/block/ide-probe.c linux.225.visws/drivers/block/ide-probe.c --- linux.225/drivers/block/ide-probe.c Mon Mar 22 12:44:18 1999 +++ linux.225.visws/drivers/block/ide-probe.c Fri Apr 16 14:09:22 1999 @@ -41,6 +41,10 @@ #include #include +#ifdef CONFIG_VISWS_HACKS +#include +#endif + #include "ide.h" static inline void do_identify (ide_drive_t *drive, byte cmd) @@ -226,6 +230,10 @@ rc = 2; /* drive refused ID */ if (!HWIF(drive)->irq) { irqs = probe_irq_off(irqs); /* get our irq number */ +#ifdef CONFIG_VISWS_HACKS +printk("VISWS HACK: setting IDE irq to %d\n", CO_IRQ_IDE); +irqs = CO_IRQ_IDE; +#endif if (irqs > 0) { HWIF(drive)->irq = irqs; /* save it for later */ irqs = probe_irq_on(); @@ -409,8 +417,12 @@ if (hwif->noprobe) return; +#ifdef CONFIG_VISWS_HACKS +printk("ide:probe_hwif... skipping CMOS probe\n"); +#else if (hwif->io_ports[IDE_DATA_OFFSET] == HD_DATA) probe_cmos_for_drives (hwif); +#endif if ((hwif->chipset != ide_4drives || !hwif->mate->present) #if CONFIG_BLK_DEV_PDC4030 && (hwif->chipset != ide_pdc4030 || hwif->channel == 0) diff -Naur linux.225/drivers/char/serial.c linux.225.visws/drivers/char/serial.c --- linux.225/drivers/char/serial.c Tue Mar 23 13:13:58 1999 +++ linux.225.visws/drivers/char/serial.c Thu Apr 15 17:43:05 1999 @@ -100,7 +100,7 @@ #undef SERIAL_DEBUG_FLOW #undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT -#define RS_STROBE_TIME (10*HZ) +#define RS_STROBE_TIME (HZ/10) #define RS_ISR_PASS_LIMIT 256 #define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? SA_SHIRQ : SA_INTERRUPT) diff -Naur linux.225/include/asm-i386/cobalt.h linux.225.visws/include/asm-i386/cobalt.h --- linux.225/include/asm-i386/cobalt.h Sun Jan 24 21:55:04 1999 +++ linux.225.visws/include/asm-i386/cobalt.h Wed Dec 31 16:00:00 1969 @@ -1,117 +0,0 @@ -#include -#ifndef __I386_COBALT_H -#define __I386_COBALT_H - -/* - * Cobalt is the system ASIC on the SGI 320 and 540 Visual Workstations - */ - -#define CO_CPU_PHYS 0xc2000000 -#define CO_APIC_PHYS 0xc4000000 - -/* see set_fixmap() and asm/fixmap.h */ -#define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU)) -#define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC)) - -/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */ -#define CO_CPU_REV 0x08 -#define CO_CPU_CTRL 0x10 -#define CO_CPU_STAT 0x20 -#define CO_CPU_TIMEVAL 0x30 - -/* CO_CPU_CTRL bits */ -#define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */ -#define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */ - -/* CO_CPU_STATUS bits */ -#define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */ - -/* CO_CPU_TIMEVAL value */ -#define CO_TIME_HZ 100000000 /* Cobalt core rate */ - -/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */ -#define CO_APIC_HI(n) (((n) * 0x10) + 4) -#define CO_APIC_LO(n) ((n) * 0x10) -#define CO_APIC_ID 0x0ffc - -/* CO_APIC_ID bits */ -#define CO_APIC_ENABLE 0x00000100 - -/* CO_APIC_LO bits */ -#define CO_APIC_LEVEL 0x08000 /* 0 = edge */ - -/* - * Where things are physically wired to Cobalt - * #defines with no board ___ are common to all (thus far) - */ -#define CO_APIC_0_5_IDE0 5 -#define CO_APIC_0_5_SERIAL 13 /* XXX not really...h/w bug! */ -#define CO_APIC_0_5_PARLL 4 -#define CO_APIC_0_5_FLOPPY 6 - -#define CO_APIC_0_6_IDE0 4 -#define CO_APIC_0_6_USB 7 /* PIIX4 USB */ - -#define CO_APIC_1_2_IDE0 4 - -#define CO_APIC_0_5_IDE1 2 -#define CO_APIC_0_6_IDE1 2 - -/* XXX */ -#define CO_APIC_IDE0 CO_APIC_0_5_IDE0 -#define CO_APIC_IDE1 CO_APIC_0_5_IDE1 -#define CO_APIC_SERIAL CO_APIC_0_5_SERIAL -/* XXX */ - -#define CO_APIC_ENET 3 /* Lithium PCI Bridge A, Device 3 */ -#define CO_APIC_8259 12 /* serial, floppy, par-l-l, audio */ - -#define CO_APIC_VIDOUT0 16 -#define CO_APIC_VIDOUT1 17 -#define CO_APIC_VIDIN0 18 -#define CO_APIC_VIDIN1 19 - -#define CO_APIC_CPU 28 /* Timer and Cache interrupt */ - -/* - * This is the "irq" arg to request_irq(), just a unique cookie. - */ -#define CO_IRQ_TIMER 0 -#define CO_IRQ_ENET 3 -#define CO_IRQ_SERIAL 4 -#define CO_IRQ_FLOPPY 6 /* Same as drivers/block/floppy.c:FLOPPY_IRQ */ -#define CO_IRQ_PARLL 7 -#define CO_IRQ_POWER 9 -#define CO_IRQ_IDE 14 -#define CO_IRQ_8259 12 - -#ifdef CONFIG_X86_VISWS_APIC -extern __inline void co_cpu_write(unsigned long reg, unsigned long v) -{ - *((volatile unsigned long *)(CO_CPU_VADDR+reg))=v; -} - -extern __inline unsigned long co_cpu_read(unsigned long reg) -{ - return *((volatile unsigned long *)(CO_CPU_VADDR+reg)); -} - -extern __inline void co_apic_write(unsigned long reg, unsigned long v) -{ - *((volatile unsigned long *)(CO_APIC_VADDR+reg))=v; -} - -extern __inline unsigned long co_apic_read(unsigned long reg) -{ - return *((volatile unsigned long *)(CO_APIC_VADDR+reg)); -} -#endif - -extern char visws_board_type; - -#define VISWS_320 0 -#define VISWS_540 1 - -extern char visws_board_rev; - -#endif diff -Naur linux.225/include/asm-i386/lithium.h linux.225.visws/include/asm-i386/lithium.h --- linux.225/include/asm-i386/lithium.h Sun Jan 24 21:56:35 1999 +++ linux.225.visws/include/asm-i386/lithium.h Wed Dec 31 16:00:00 1969 @@ -1,45 +0,0 @@ -#ifndef __I386_LITHIUM_H -#define __I386_LITHIUM_H - -#include - -/* - * Lithium is the I/O ASIC on the SGI 320 and 540 Visual Workstations - */ - -#define LI_PCI_A_PHYS 0xfc000000 /* Enet is dev 3 */ -#define LI_PCI_B_PHYS 0xfd000000 /* PIIX4 is here */ - -/* see set_fixmap() and asm/fixmap.h */ -#define LI_PCIA_VADDR (fix_to_virt(FIX_LI_PCIA)) -#define LI_PCIB_VADDR (fix_to_virt(FIX_LI_PCIB)) - -/* Not a standard PCI? (not in linux/pci.h) */ -#define LI_PCI_BUSNUM 0x44 /* lo8: primary, hi8: sub */ -#define LI_PCI_INTEN 0x46 - -#ifdef CONFIG_X86_VISWS_APIC -/* More special purpose macros... */ -extern __inline void li_pcia_write16(unsigned long reg, unsigned short v) -{ - *((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v; -} - -extern __inline unsigned short li_pcia_read16(unsigned long reg) -{ - return *((volatile unsigned short *)(LI_PCIA_VADDR+reg)); -} - -extern __inline void li_pcib_write16(unsigned long reg, unsigned short v) -{ - *((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v; -} - -extern __inline unsigned short li_pcib_read16(unsigned long reg) -{ - return *((volatile unsigned short *)(LI_PCIB_VADDR+reg)); -} -#endif - -#endif - diff -Naur linux.225/include/asm-i386/sgi-cobalt.h linux.225.visws/include/asm-i386/sgi-cobalt.h --- linux.225/include/asm-i386/sgi-cobalt.h Wed Dec 31 16:00:00 1969 +++ linux.225.visws/include/asm-i386/sgi-cobalt.h Fri Apr 16 14:50:18 1999 @@ -0,0 +1,131 @@ +#include +#ifndef __I386_SGI_COBALT_H +#define __I386_SGI_COBALT_H + +/* + * Cobalt SGI Visual Workstation system ASIC + */ + +#define CO_CPU_PHYS 0xc2000000 +#define CO_APIC_PHYS 0xc4000000 + +/* see set_fixmap() and asm/fixmap.h */ +#define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU)) +#define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC)) + +/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */ +#define CO_CPU_REV 0x08 +#define CO_CPU_CTRL 0x10 +#define CO_CPU_STAT 0x20 +#define CO_CPU_TIMEVAL 0x30 + +/* CO_CPU_CTRL bits */ +#define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */ +#define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */ + +/* CO_CPU_STATUS bits */ +#define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */ + +/* CO_CPU_TIMEVAL value */ +#define CO_TIME_HZ 100000000 /* Cobalt core rate */ + +/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */ +#define CO_APIC_HI(n) (((n) * 0x10) + 4) +#define CO_APIC_LO(n) ((n) * 0x10) +#define CO_APIC_ID 0x0ffc + +/* CO_APIC_ID bits */ +#define CO_APIC_ENABLE 0x00000100 + +/* CO_APIC_LO bits */ +#define CO_APIC_LEVEL 0x08000 /* 0 = edge */ + +/* + * Where things are physically wired to Cobalt + * #defines with no board ___ are common to all (thus far) + */ +#define CO_APIC_0_5_IDE0 5 + +#define CO_APIC_0_6_IDE0 4 +#define CO_APIC_0_6_USB 7 /* PIIX4 USB */ + +#define CO_APIC_1_2_IDE0 4 + +#define CO_APIC_0_5_IDE1 2 +#define CO_APIC_0_6_IDE1 2 + +#define CO_APIC_8259 12 /* serial, floppy, par-l-l, audio */ + +/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */ +/* CO_APIC_PCI_ -- matches h/w diagrams */ +#define CO_APIC_PCIA_A0 0 +#define CO_APIC_PCIA_A1 1 +#define CO_APIC_PCIA_A3 3 +#define CO_APIC_PCIA_B 5 +#define CO_APIC_PCIA_C 6 +#define CO_APIC_INTEL_ENET CO_APIC_PCIA_A3 + +/* Lithium PCI Bridge B -- "the one with PIIX4" */ +#define CO_APIC_PIIX4_USB 7 + +#define CO_APIC_PCIB_A0 8 +#define CO_APIC_PCIB_A1 9 +#define CO_APIC_PCIB_A2 10 +#define CO_APIC_PCIB_A3 11 +#define CO_APIC_PCIB_B 13 +#define CO_APIC_PCIB_C 14 +#define CO_APIC_PCIB_D 15 + +#define CO_APIC_VIDOUT0 16 +#define CO_APIC_VIDOUT1 17 +#define CO_APIC_VIDIN0 18 +#define CO_APIC_VIDIN1 19 + +#define CO_APIC_LI_AUDIO 22 + +#define CO_APIC_CPU 28 /* Timer and Cache interrupt */ +#define CO_APIC_NMI 29 +#define CO_APIC_LAST CO_APIC_NMI + +/* + * This is how irqs are assigned on the Visual Workstation. + * Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU). + * All other devices (including PCI) go to Cobalt and are irq's 16 on up. + */ +#define CO_IRQ_APIC0 16 /* irq of apic entry 0 */ +#define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0) +#define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */ +#define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */ +#define CO_IRQ_IDE 14 +#define CO_IRQ_8259 CO_IRQ(CO_APIC_8259) + +#ifdef CONFIG_X86_VISWS_APIC +extern __inline void co_cpu_write(unsigned long reg, unsigned long v) +{ + *((volatile unsigned long *)(CO_CPU_VADDR+reg))=v; +} + +extern __inline unsigned long co_cpu_read(unsigned long reg) +{ + return *((volatile unsigned long *)(CO_CPU_VADDR+reg)); +} + +extern __inline void co_apic_write(unsigned long reg, unsigned long v) +{ + *((volatile unsigned long *)(CO_APIC_VADDR+reg))=v; +} + +extern __inline unsigned long co_apic_read(unsigned long reg) +{ + return *((volatile unsigned long *)(CO_APIC_VADDR+reg)); +} +#endif + +extern char visws_board_type; + +#define VISWS_320 0 +#define VISWS_540 1 + +extern char visws_board_rev; + +#endif diff -Naur linux.225/include/asm-i386/sgi-lithium.h linux.225.visws/include/asm-i386/sgi-lithium.h --- linux.225/include/asm-i386/sgi-lithium.h Wed Dec 31 16:00:00 1969 +++ linux.225.visws/include/asm-i386/sgi-lithium.h Fri Apr 16 14:50:24 1999 @@ -0,0 +1,56 @@ +#ifndef __I386_SGI_LITHIUM_H +#define __I386_SGI_LITHIUM_H + +#include + +/* + * Lithium is the SGI Visual Workstation I/O ASIC + */ + +#define LI_PCI_A_PHYS 0xfc000000 /* Enet is dev 3 */ +#define LI_PCI_B_PHYS 0xfd000000 /* PIIX4 is here */ + +/* see set_fixmap() and asm/fixmap.h */ +#define LI_PCIA_VADDR (fix_to_virt(FIX_LI_PCIA)) +#define LI_PCIB_VADDR (fix_to_virt(FIX_LI_PCIB)) + +/* Not a standard PCI? (not in linux/pci.h) */ +#define LI_PCI_BUSNUM 0x44 /* lo8: primary, hi8: sub */ +#define LI_PCI_INTEN 0x46 + +/* LI_PCI_INTENT bits */ +#define LI_INTA_0 0x0001 +#define LI_INTA_1 0x0002 +#define LI_INTA_2 0x0004 +#define LI_INTA_3 0x0008 +#define LI_INTA_4 0x0010 +#define LI_INTB 0x0020 +#define LI_INTC 0x0040 +#define LI_INTD 0x0080 + + +#ifdef CONFIG_X86_VISWS_APIC +/* More special purpose macros... */ +extern __inline void li_pcia_write16(unsigned long reg, unsigned short v) +{ + *((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v; +} + +extern __inline unsigned short li_pcia_read16(unsigned long reg) +{ + return *((volatile unsigned short *)(LI_PCIA_VADDR+reg)); +} + +extern __inline void li_pcib_write16(unsigned long reg, unsigned short v) +{ + *((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v; +} + +extern __inline unsigned short li_pcib_read16(unsigned long reg) +{ + return *((volatile unsigned short *)(LI_PCIB_VADDR+reg)); +} +#endif + +#endif + diff -Naur linux.225/include/asm-i386/sgi-piix.h linux.225.visws/include/asm-i386/sgi-piix.h --- linux.225/include/asm-i386/sgi-piix.h Wed Dec 31 16:00:00 1969 +++ linux.225.visws/include/asm-i386/sgi-piix.h Fri Apr 16 14:54:04 1999 @@ -0,0 +1,113 @@ +#ifndef __I386_SGI_PIIX_H +#define __I386_SGI_PIIX_H + +/* + * PIIX4 as used on SGI Visual Workstations + */ + +/* + * The PCI bus with PIIX4. + * XXX bus numbering should be virtualized?! + */ +#define PIIX4_BUS 0 + +#define PIIX_PM_START 0x0F80 + +#define SIO_GPIO_START 0x0FC0 + +#define SIO_PM_START 0x0FC8 + +#define PMBASE PIIX_PM_START +#define GPIREG0 (PMBASE+0x30) +#define GPIREG(x) (GPIREG0+((x)/8)) +#define GPIBIT(x) (1 << ((x)%8)) + +#define PIIX_GPI_BD_ID1 18 +#define PIIX_GPI_BD_ID2 19 +#define PIIX_GPI_BD_ID3 20 +#define PIIX_GPI_BD_ID4 21 +#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1) +#define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \ + GPIBIT(PIIX_GPI_BD_ID2) | \ + GPIBIT(PIIX_GPI_BD_ID3) | \ + GPIBIT(PIIX_GPI_BD_ID4) ) + +#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8) + +#define SIO_INDEX 0x2e +#define SIO_DATA 0x2f + +#define SIO_DEV_SEL 0x7 +#define SIO_DEV_ENB 0x30 +#define SIO_DEV_MSB 0x60 +#define SIO_DEV_LSB 0x61 + +#define SIO_GP_DEV 0x7 + +#define SIO_GP_BASE SIO_GPIO_START +#define SIO_GP_MSB (SIO_GP_BASE>>8) +#define SIO_GP_LSB (SIO_GP_BASE&0xff) + +#define SIO_GP_DATA1 (SIO_GP_BASE+0) + +#define SIO_PM_DEV 0x8 + +#define SIO_PM_BASE SIO_PM_START +#define SIO_PM_MSB (SIO_PM_BASE>>8) +#define SIO_PM_LSB (SIO_PM_BASE&0xff) +#define SIO_PM_INDEX (SIO_PM_BASE+0) +#define SIO_PM_DATA (SIO_PM_BASE+1) + +#define SIO_PM_FER2 0x1 + +#define SIO_PM_GP_EN 0x80 + + + +/* + * This is the dev/reg where generating a config cycle will + * result in a PCI special cycle. + */ +#define SPECIAL_DEV 0xff +#define SPECIAL_REG 0x00 + +/* + * PIIX4 needs to see a special cycle with the following data + * to be convinced the processor has gone into the stop grant + * state. PIIX4 insists on seeing this before it will power + * down a system. + */ +#define PIIX_SPECIAL_STOP 0x00120002 + +#define PIIX4_RESET_PORT 0xcf9 +#define PIIX4_RESET_VAL 0x6 + +#define PMSTS_PORT 0xf80 // 2 bytes PM Status +#define PMEN_PORT 0xf82 // 2 bytes PM Enable +#define PMCNTRL_PORT 0xf84 // 2 bytes PM Control + +#define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state + +/* + * PMSTS and PMEN I/O bit definitions. + * (Bits are the same in both registers) + */ +#define PM_STS_RSM (1<<15) // Resume Status +#define PM_STS_PWRBTNOR (1<<11) // Power Button Override +#define PM_STS_RTC (1<<10) // RTC status +#define PM_STS_PWRBTN (1<<8) // Power Button Pressed? +#define PM_STS_GBL (1<<5) // Global Status +#define PM_STS_BM (1<<4) // Bus Master Status +#define PM_STS_TMROF (1<<0) // Timer Overflow Status. + +/* + * Stop clock GPI register + */ +#define PIIX_GPIREG0 (0xf80 + 0x30) + +/* + * Stop clock GPI bit in GPIREG0 + */ +#define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in + +#endif