Re: Help - IR Genlock problems!!

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Performer Mailing List (perflist++at++vr.mme.wsu.edu)
Fri, 26 Sep 1997 03:17:39 -0700


Joerg:

I figured I needed some special cable for the genlocking since the sync
output was coming through the green of the monitor output. I used a
pigtail (SGI monitor connector on one end and RGB BNCs at the other). I
used the "G" BNC to the Genlock in. I am assuming that is similar to
the other cable you described to me.

Thanks for the pictures - of course there are no labels on the boards!!

Jay

Joerg Wallmersperger wrote:
>
> Jay,
>
> are you aware, that you need a special cable for genlocking Onyx2
> systems?
>
> There is a special 13W3 cable, which has 2 separate BNC cable outputs for
> HSYNC and VSYNC. Put the white cable (I think) into the genlock-in of the
> other pipe and put the 75 Ohm terminator on Genlock Loop Through. Genlock
> Loop Through is the bottommost BNC connector, Genlock In is the one above
> - just in case there is no label :-)
>
> I attached a dg5 gif picture. As you can see, there are no seperate SYNC
> outputs like Onyx IR systems used to have.
>
> I think this cable is shipped with all Multipipe Onyx2 configurations. In
> case you don't have it, the SGI Partnumber is 018-0634-001. I also
> attached a picture of this one.
>
> As stated below, the ircombine issues seem to be correct.
>
> Greetings
>
> Joerg
>
> On Sep 25, 11:08pm, Performer Mailing List wrote:
> } Subject: Help - IR Genlock problems!!
> } I have a 2-pipe Onyx2 and am trying to use the VR4 HMD in stereo mode.
> } I have tried all the previous suggestions on IR genlocks. The format I
> } need is 640x486_30i. I set both my pipes to the same format. Pipe 1
> } has EXTERNAL sync. I am using the green of the RGB output from one of
> } the channels of pipe 0 as the sync being sent to the Genlock in of pipe
> } 1. Pipe 1 genlock "loop-through" is terminated.
> }
> } gfxinfo tells me that pipe 0 genlock is false and pipe 1 genlock is
> } true. However, my Performer application still complains that the pipes
> } are not genlocked.
> }
> } My left and right views are not in sync (I am assuming this is because
> } of Genlocking problems!)
> }
> } Help!!
> }
> } Jay
> }
> }
> }
> }
> }
> }
> }
> }
> } Javier Castellar wrote:
> } >
> } > > I am using pipes 0 and 1 at 2++at++1280x1024_60 and pipe 2 at
> 8++at++640x480_60, but I
> } > > have no better luck when all pipes are at 1280x1024++at++60.
> } > >
> } > > Pipe 0's vertical sync is cabled to Pipe 1's genlock in. Pipe 1's
> gelock out
> } > > is cabled to Pipe 2's genlock in. Pipe 2's genlock out is
> terminated. A
> } > > scope shows that Pipe 2's genlock out is getting a 60Hz pulse, as
> expected,
> } > > i.e., no obvious signal problem through the pipes.
> } > >
> } > > Using ircombine, pipe 0's sync is set INTERNAL; pipe 1 and 2's
> syncs are set
> } > > EXTERNAL.
> } >
> } > You have to provide as well the external sync format.
> } > In the "Edit Globals" window, under the sync type (INTERNAL in first
> pipe and
> } > EXTERNAL in second and third) you have to type 1280x1024_60.vfo.
> } >
> } > sync: EXTERNAL
> } > sync format: <the format to sync>.vfo
> } >
> } > The iR DG4 has the ability to genlock with nearly any signal, as soon
> as you
> } > said so.
> } >
> } > In order to check if it is genlocked please use:
> } >
> } > /usr/gfx/gfxinfo -v | grep Sync
> } >
> } > I will be in IITSEC during next week, if is more urgent try to
> contact my
> } > admin.
> } >
> } > It know that it works, I have personally genlocked our 3 pipe iR, a 3
> pipe
> } > Onyx2 and nice 4 pipe Onyx2.
> } >
> } > Try to genlock first couple by couple (i.e. 0->1 ) to be sure the
> cables are
> } > right, one by one. It will reduce the number of variables.
> } >
> } > Remember to terminate the last genlock out.
> } >
> } > -Javier
> } >
> } > --
> } >
> *************************************************************************
> } > * Javier Castellar Arribas * Email:
> javier++at++asd.sgi.com *
> } > * * Vmail:
> 3-1589 *
> } > * Member of Technical Staff * Phone: 415-933-1589 / 2108
> (lab) *
> } > * Core Design - Applied Engineering * Fax:
> 415-964-8671 *
> } > * Advanced Systems Division * MailStop:
> 8L-800 *
> } >
> *************************************************************************
> } > * Silicon Graphics Inc.
> *
> } > * 2011 N. Shoreline Boulevard,
> *
> } > * Mountain View, California 94043-1386, USA
> *
> } >
> *************************************************************************
> } > "Violence is the last refuge of the incompetent"
> } > Hardin Seldon
> } >
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> }-- End of excerpt from Performer Mailing List
>
> --
> Joerg Wallmersperger, System Engineer
> Silicon Graphics GmbH, Am Hochacker 3, 85630 Grasbrunn
> E-mail: joerg++at++munich.sgi.com
> Tel.: 089-46108314 (US: 49.89.46108314)
> Fax.: 089-46107314 (US: 49.89.46107314)
> http://reality.sgi.com/joerg_munich
>
> ---------------------------------------------------------------
> [Image] [Image]
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