Help - IR Genlock problems!!

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Performer Mailing List (perflist++at++vr.mme.wsu.edu)
Thu, 25 Sep 1997 23:08:07 -0700

I have a 2-pipe Onyx2 and am trying to use the VR4 HMD in stereo mode.
I have tried all the previous suggestions on IR genlocks. The format I
need is 640x486_30i. I set both my pipes to the same format. Pipe 1
has EXTERNAL sync. I am using the green of the RGB output from one of
the channels of pipe 0 as the sync being sent to the Genlock in of pipe
1. Pipe 1 genlock "loop-through" is terminated.

gfxinfo tells me that pipe 0 genlock is false and pipe 1 genlock is
true. However, my Performer application still complains that the pipes
are not genlocked.

My left and right views are not in sync (I am assuming this is because
of Genlocking problems!)

Help!!

Jay

Javier Castellar wrote:
>
> > I am using pipes 0 and 1 at 2++at++1280x1024_60 and pipe 2 at 8++at++640x480_60, but I
> > have no better luck when all pipes are at 1280x1024++at++60.
> >
> > Pipe 0's vertical sync is cabled to Pipe 1's genlock in. Pipe 1's gelock out
> > is cabled to Pipe 2's genlock in. Pipe 2's genlock out is terminated. A
> > scope shows that Pipe 2's genlock out is getting a 60Hz pulse, as expected,
> > i.e., no obvious signal problem through the pipes.
> >
> > Using ircombine, pipe 0's sync is set INTERNAL; pipe 1 and 2's syncs are set
> > EXTERNAL.
>
> You have to provide as well the external sync format.
> In the "Edit Globals" window, under the sync type (INTERNAL in first pipe and
> EXTERNAL in second and third) you have to type 1280x1024_60.vfo.
>
> sync: EXTERNAL
> sync format: <the format to sync>.vfo
>
> The iR DG4 has the ability to genlock with nearly any signal, as soon as you
> said so.
>
> In order to check if it is genlocked please use:
>
> /usr/gfx/gfxinfo -v | grep Sync
>
> I will be in IITSEC during next week, if is more urgent try to contact my
> admin.
>
> It know that it works, I have personally genlocked our 3 pipe iR, a 3 pipe
> Onyx2 and nice 4 pipe Onyx2.
>
> Try to genlock first couple by couple (i.e. 0->1 ) to be sure the cables are
> right, one by one. It will reduce the number of variables.
>
> Remember to terminate the last genlock out.
>
> -Javier
>
> --
> *************************************************************************
> * Javier Castellar Arribas * Email: javier++at++asd.sgi.com *
> * * Vmail: 3-1589 *
> * Member of Technical Staff * Phone: 415-933-1589 / 2108 (lab) *
> * Core Design - Applied Engineering * Fax: 415-964-8671 *
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