|To:||Donald Becker <becker@xxxxxxxxx>|
|Subject:||Re: RFC: NAPI packet weighting patch|
|From:||Chris Friesen <cfriesen@xxxxxxxxxx>|
|Date:||Tue, 21 Jun 2005 22:44:16 -0600|
|Cc:||Andi Kleen <ak@xxxxxxx>, Rick Jones <rick.jones2@xxxxxx>, netdev@xxxxxxxxxxx, davem@xxxxxxxxxx|
|User-agent:||Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.6) Gecko/20040115|
Donald Becker wrote:
On Wed, 22 Jun 2005, Andi Kleen wrote:While much has changed since then, the same basic parameters remain - cache line sizeIn 96 we had 32 byte cache lines. These days 64-128 are common, with some 256 byte cache line systems around.Good point. I believe that the most common line size is 64 bytes for L1 cache.
If I recall, G4 chips are 32 bytes, and G5s are 128 bytes. Most current x86 chips are 64 bytes though.
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