On Fri, Jun 03, 2005 at 11:07:01PM +0200, Edgar E Iglesias wrote:
> > > Yes, in tg3, rx buffers are replenished and put back into the ring
> > > as completed packets are taken off the ring. But we don't tell the
> > > chip about these new buffers until we get to the end of the loop,
> > > potentially after a full quota of packets.
> >
> > Which makes a lot more sense, since you'd rather do one MMIO write
> > at the end of the loop than one per iteration, especially if your
> > MMIO read (flush) latency is high. (Any subsequent MMIO read will
> > have to flush out all pending writes, which'll be slow if there's
> > a lot of writes still in the queue.)
>
> Maybe it would be better to put a fixed weight at this level, return
> the descriptors to the HW after every X packets. That way you
> can keep the NAPI weight at 64 (or what ever) and still give back
> descriptors to HW more often.
For this scheme to make any difference at all, the RX ring must be
overflowing in the case where we refill the RX ring only once every
64 packets.
If the RX ring _is_ overflowing but the system is otherwise capable of
keeping up with the receive rate (i.e. the packet service times as seen
by the NIC have a high variance), simply make the RX ring bigger.
I don't see what's going on.
--L
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