Re: RFC: NAPI packet weighting patch

[jamal <hadi@xxxxxxxxxx>]

On Fri, 2005-03-06 at 13:35 -0700, Michael Chan wrote:
> On Fri, 2005-06-03 at 22:59 +0200, Lennert Buytenhek wrote:

> > Which makes a lot more sense, since you'd rather do one MMIO write
> > at the end of the loop than one per iteration, especially if your
> > MMIO read (flush) latency is high.  (Any subsequent MMIO read will
> > have to flush out all pending writes, which'll be slow if there's
> > a lot of writes still in the queue.)
> > 
> I agree on the merit of issuing only one IO at the end. What I'm saying
> is that doing so will make it similar to e1000 where all the buffers are
> replenished at the end. Isn't that so or am I missing something?
> 

I think the main issue would be a lot less CPU used in your case
(because of the single MMIO).

> By the way, in tg3 there is a buffer replenishment threshold programmed
> to the chip and is currently set at rx_pending / 8 (200/8 = 25). This
> means that the chip will replenish 25 rx buffers at a time.
> 

So when you write the MMIO, 25 buffers are replenished or is this auto
magically happening in the background? Sounds like a neat feature either
way.

cheers,
jamal