From: "Michael Chan" <mchan@xxxxxxxxxxxx>
Subject: Re: tg3 support broken on PPC, a workaround
Date: Tue, 10 May 2005 09:52:46 -0700
> In the new code, the DMA write bursts will disconnect at multiples of
> cache lines instead of 1 cache line. And DMA read bursts will not
> disconnect at cache line boundaries.
We really should be disconnecting at single cacheline boundaries
on RISC systems. The PCI controllers on RISC machines are
going to disconnect the tg3 when it crosses a cache line
boundary, so all these setting do is waste PCI bandwidth.
From the sparc64 PCI controller programmer's manual:
"When a DMA burst transfer attempts to go past a cache line (64B)
boundary, U2P generates a disconnect. This should cause the
master device to attempt the transaction again beginning at the
address of the next untransferred data."
Most other RISC systems have PCI controllers which
behave similarly if not identically, although there
are probably some exceptions.
Anyways, it is clear this code needs to change. :-)