| To: | "David S. Miller" <davem@xxxxxxxxxxxxx> |
|---|---|
| Subject: | [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750 |
| From: | "Michael Chan" <mchan@xxxxxxxxxxxx> |
| Date: | Sun, 20 Mar 2005 23:48:13 -0800 |
| Cc: | netdev@xxxxxxxxxxx |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| Thread-index: | AcUQenBthEVwCOEDSUG7grDnD7JTOgdadRIAAABhWpAAAGS18AAARWAgAABS6GA= |
| Thread-topic: | [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750 |
Add unstable PLL clock workaround for 5750 Ax and Bx devices. The workaround code is run just before entering D3hot state. Signed-off-by: Michael Chan <mchan@xxxxxxxxxxxx>
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