| To: | "David S. Miller" <davem@xxxxxxxxxxxxx> |
|---|---|
| Subject: | [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt |
| From: | "Michael Chan" <mchan@xxxxxxxxxxxx> |
| Date: | Sun, 20 Mar 2005 23:26:26 -0800 |
| Cc: | netdev@xxxxxxxxxxx |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| Thread-index: | AcUQenBthEVwCOEDSUG7grDnD7JTOgdadRIAAABhWpA= |
| Thread-topic: | [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt |
Add register read of PCI state register in tg3_interrupt() if status block's updated bit is not set. This will flush the status block and confirm whether the interrupt is ours or not. PCI ordering rules allow the interrupt to arrive at the CPU ahead of the status block that may be posted at the chipset. Signed-off-by: Michael Chan <mchan@xxxxxxxxxxxx>
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