| To: | "David S. Miller" <davem@xxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: [PATCH] use mmiowb in tg3.c |
| From: | Jesse Barnes <jbarnes@xxxxxxx> |
| Date: | Thu, 21 Oct 2004 22:01:34 -0500 |
| Cc: | Jesse Barnes <jbarnes@xxxxxxxxxxxx>, akpm@xxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, netdev@xxxxxxxxxxx, jgarzik@xxxxxxxxx, gnb@xxxxxxx, akepner@xxxxxxx |
| In-reply-to: | <20041021164007.4933b10b.davem@xxxxxxxxxxxxx> |
| References: | <200410211613.19601.jbarnes@xxxxxxxxxxxx> <200410211628.06906.jbarnes@xxxxxxxxxxxx> <20041021164007.4933b10b.davem@xxxxxxxxxxxxx> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| User-agent: | KMail/1.7 |
On Thursday, October 21, 2004 6:40 pm, David S. Miller wrote: > On Thu, 21 Oct 2004 16:28:06 -0700 > > Jesse Barnes <jbarnes@xxxxxxxxxxxx> wrote: > > This patch originally from Greg Banks. Some parts of the tg3 driver > > depend on PIO writes arriving in order. This patch ensures that in two > > key places using the new mmiowb macro. This not only prevents bugs (the > > queues can be corrupted), but is much faster than ensuring ordering using > > PIO reads (which involve a few round trips to the target bus on some > > platforms). > > Do other PCI systems which post PIO writes also potentially reorder > them just like this SGI system does? Just trying to get this situation > straight in my head. The HP guys claim that theirs don't, but PPC does, afaik. And clearly any large system that posts PCI writes has the *potential* of reordering them. Thanks, Jesse |
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