| To: | akepner@xxxxxxx |
|---|---|
| Subject: | Re: [PATCH] use mmiowb in tg3.c |
| From: | Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx> |
| Date: | Fri, 22 Oct 2004 12:07:24 +1000 |
| Cc: | "David S. Miller" <davem@xxxxxxxxxxxxx>, Jesse Barnes <jbarnes@xxxxxxxxxxxx>, Andrew Morton <akpm@xxxxxxxx>, Linux Kernel list <linux-kernel@xxxxxxxxxxxxxxx>, netdev@xxxxxxxxxxx, Jeff Garzik <jgarzik@xxxxxxxxx>, gnb@xxxxxxx |
| In-reply-to: | <Pine.LNX.4.33.0410211826480.392-100000@xxxxxxxxxxxxxxxxxxxxx> |
| References: | <Pine.LNX.4.33.0410211826480.392-100000@xxxxxxxxxxxxxxxxxxxxx> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
On Fri, 2004-10-22 at 11:33, akepner@xxxxxxx wrote: > On Fri, 22 Oct 2004, Benjamin Herrenschmidt wrote: > > > ... > > Typically, our normal "light" write barrier doesn't reorder between > > cacheable > > and non-cacheable (MMIO) stores, which is why we had to put some heavy sync > > barrier in our MMIO writes macros. > > ... > > Do you mean "impose order" rather than "reorder" here? Right. Ben. |
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