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Re: The ultimate TOE design

To: Jeff Garzik <jgarzik@xxxxxxxxx>, "David S. Miller" <davem@xxxxxxxxxxxxx>
Subject: Re: The ultimate TOE design
From: Lincoln Dale <ltd@xxxxxxxxx>
Date: Thu, 16 Sep 2004 19:29:43 +1000
Cc: alan@xxxxxxxxxxxxxxxxxxx, paul@xxxxxxxx, netdev@xxxxxxxxxxx, leonid.grossman@xxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx
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not that i disagree with the general idea and rationale, but reality is what it is today for some reasons:

At 07:23 AM 16/09/2004, Jeff Garzik wrote:
        Jeff, who would love to have a bunch of Athlons
        on PCI cards to play with.

. . . this ignore the realities of power restrictions of PCI today . . .
sure, one could create a PCI card that takes a power-connector, but that don't scale so well either . . .

At 07:29 AM 16/09/2004, David S. Miller wrote:
I think a better goal is "offload 90+% of the net stack cost" which
is effectively what TSO does on the send side.

This is why these discussions are so circular.

TSO works on LAN-like environments (zero latency, minimal drop), it doesn't work so well across the internet . . .

i believe that there are better alternatives than TSO, but it involves NICs having decent scatter-gather DMA engines and being able to be handled multiple transactions (packets/frames) at once. in theory, NICs like tg2/tg3 should be capable of implementing something like this -- if one could get to the ucode on the embedded cores.

at least with PCI Express the general architecture of a PC starts to have a hope of keeping up with Moore's law. the same couldn't be said prior to DDR-SDRAM and higher front-side-bus frequencies.



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