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Re: The ultimate TOE design

To: Netdev <netdev@xxxxxxxxxxx>
Subject: Re: The ultimate TOE design
From: "Bill Rugolsky Jr." <brugolsky@xxxxxxxxxxxxxxxxxxxxxxxxx>
Date: Wed, 15 Sep 2004 16:31:22 -0400
Cc: Jeff Garzik <jgarzik@xxxxxxxxx>, David Stevens <dlstevens@xxxxxxxxxx>
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On Wed, Sep 15, 2004 at 02:11:04PM -0600, David Stevens wrote:
> If the PCI bus is too slow, or MTU's too small, wouldn't
> it be better to fix those directly and use a fast host processor that can
> also do other things when not needed for networking? And why have
> memory on a NIC that can't be used by other things?
 
I tend to agree.

Referring to the Opteron with its per-CPU memory controller, Robert Olsson
just wrote in the "TX performance of Intel 82546" thread:

  This is a little breakthrough as we for the first time see some
  aggregated performance with packet forwarding and got something in
  return for all multiprocessor efforts.

  IMO this is much more important then the last percent of performance
  of pps numbers.

In 2005, we'll have commodity dual-core packages, making a four-core
(dual-CPU) system available at an attractive price point.  The number
will rise dramatically after that.  I don't really think CPU cycles are
the problem.  A  useful reason I can see for "offloading" is isolation of
concerns, e.g., locking, real-time latencies, security, etc.  But then,
why not run something like the Xen2 virtual machine environment?

Regards,

        Bill Rugolsky

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