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Re: FW: Submission for S2io 10GbE driver

To: Andi Kleen <ak@xxxxxxx>
Subject: Re: FW: Submission for S2io 10GbE driver
From: Anton Blanchard <anton@xxxxxxxxx>
Date: Thu, 5 Feb 2004 12:51:49 +1100
Cc: Leonid Grossman <leonid.grossman@xxxxxxxx>, netdev@xxxxxxxxxxx, raghava.vatsavayi@xxxxxxxx, iod00d@xxxxxx
In-reply-to: <20040205023209.4abf2342.ak@xxxxxxx>
References: <20040123232209.2739e6aa.ak@xxxxxxx> <004201c3eb5f$ac4e9f00$740efea9@xxxxxxxxxxxx> <20040205023209.4abf2342.ak@xxxxxxx>
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> > 1) We did't find quad word memory operations(writeq and readq) on PCI
> > bus for PPC64 architecture.
> 
> That's a bug in ppc64 then. Can you complain to them?  I would go
> ahead and just use them in the driver unconditionally and wait for the
> ppc64 to fix it. Or just add them there, it's probably simple.

Yep ppc64 should define them. If you are submitting a driver for
inclusion in 2.6 leave these bits out, its my fault they arent defined
and I'll get them added in.

Turns out lots of architectures are missing these, I'll fire an email
off to linux-arch about it.

> > On a little endian m/c like IA32 also writel writes same values in a
> > similar manner as shown above. 
> > So the question is -
> > Do all big endian machines with linux OS swap the values and write in
> > little endian format?? 
> 
> I hope not.

Thats how all big endian platforms work. in* and out*, read* and write*
byteswap. 

> > 3)In PPC64 architecture dma_addr_t is u32, unlike remaining 64 bit
> > architectures where it is defined as u64. Because
> > of this we have to deal separately for PP64. 
> > So any suggestions will be useful, .i.e. generally how PPC64 developers
> > deal with this?
> 
> You could just use u64 in your structure definitions for now.

Its up to the architecture as to what a dma_addr_t looks like. On our
current machines we only support operating through the IOMMU, so all
PCI bus address are in fact 32bit. Most drivers dont care how big a
dma_addr_t is, is there something you are doing that does?

Anton

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