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Re: Info: NAPI performance at "low" loads

To: Alan Cox <alan@xxxxxxxxxxxxxxxxxxx>
Subject: Re: Info: NAPI performance at "low" loads
From: ebiederm@xxxxxxxxxxxx (Eric W. Biederman)
Date: 19 Sep 2002 08:58:49 -0600
Cc: "David S. Miller" <davem@xxxxxxxxxx>, hadi@xxxxxxxxxx, akpm@xxxxxxxxx, manfred@xxxxxxxxxxxxxxxx, netdev@xxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx
In-reply-to: <1032371453.20463.139.camel@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
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Alan Cox <alan@xxxxxxxxxxxxxxxxxxx> writes:

> On Wed, 2002-09-18 at 18:27, Eric W. Biederman wrote:
> > Plus I have played with calibrating the TSC with outb to port
> > 0x80 and there was enough variation that it was unuseable.  On some
> > newer systems it would take twice as long as on some older ones.
> 
> port 0x80 isnt going to PCI space.

Agreed.  It isn't going anywhere, and it takes it a while to recogonize
that.
 
> x86 generally posts mmio write but not io write. Thats quite measurable.

The difference timing difference between posted and non-posted writes
I can see.

Eric


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