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References: [ +subject:/^(?:^\s*(re|sv|fwd|fw)[\[\]\d]*[:>-]+\s*)*\[TG3\]\:\s+Add\s+hw\s+coalescing\s+infrastructure\.\s*$/: 8 ]

Total 8 documents matching your query.

1. [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: . Miller" <davem@xxxxxxxxxxxxx>
Date: Wed, 11 May 2005 14:15:30 -0700 (PDT)
Ok, now that we have the tagged status stuff sorted I began to work on putting the hw mitigation bits back into the driver. The discussion on the DMA rw-ctrl settings is still ongoing, but I will get
/archives/netdev/2005-05/msg00436.html (15,035 bytes)

2. Re: [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: xx>
Date: Wed, 11 May 2005 14:17:36 -0700
These registers are still defined for 5705_PLUS chips, only the maximum value has been reduced to 255. So we're ok. Yes, and MTU size dependent too. But we may not want to coalesce the same way when
/archives/netdev/2005-05/msg00440.html (8,853 bytes)

3. Re: [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: e Melo <arnaldo.melo@xxxxxxxxx>
Date: Wed, 11 May 2005 19:28:19 -0700 (PDT)
That's a good point. I think it would be wise for us to try and come up with a dynamic mitigation algorithm that is as MTU and link speed agnostic as possible. One thing to note is that what we're re
/archives/netdev/2005-05/msg00450.html (17,510 bytes)

4. Re: [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: lerman <michael@xxxxxxxxxxxxxx>
Date: Thu, 12 May 2005 09:53:53 +0200
Size of RX-ring is also to be taken to account. You probably have to design for samllest packets otherwise you risk RX-ring overrun and packet drop. Yes. Cheers. --ro
/archives/netdev/2005-05/msg00458.html (9,216 bytes)

5. [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: "David S. Miller" <davem@xxxxxxxxxxxxx>
Date: Wed, 11 May 2005 14:15:30 -0700 (PDT)
Ok, now that we have the tagged status stuff sorted I began to work on putting the hw mitigation bits back into the driver. The discussion on the DMA rw-ctrl settings is still ongoing, but I will get
/archives/netdev/2005-05/msg01725.html (15,035 bytes)

6. Re: [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: "Michael Chan" <mchan@xxxxxxxxxxxx>
Date: Wed, 11 May 2005 14:17:36 -0700
These registers are still defined for 5705_PLUS chips, only the maximum value has been reduced to 255. So we're ok. Yes, and MTU size dependent too. But we may not want to coalesce the same way when
/archives/netdev/2005-05/msg01729.html (8,929 bytes)

7. Re: [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: "David S. Miller" <davem@xxxxxxxxxxxxx>
Date: Wed, 11 May 2005 19:28:19 -0700 (PDT)
That's a good point. I think it would be wise for us to try and come up with a dynamic mitigation algorithm that is as MTU and link speed agnostic as possible. One thing to note is that what we're re
/archives/netdev/2005-05/msg01739.html (17,670 bytes)

8. Re: [TG3]: Add hw coalescing infrastructure. (score: 1)
Author: Robert Olsson <Robert.Olsson@xxxxxxxxxxx>
Date: Thu, 12 May 2005 09:53:53 +0200
Size of RX-ring is also to be taken to account. You probably have to design for samllest packets otherwise you risk RX-ring overrun and packet drop. Yes. Cheers. --ro
/archives/netdev/2005-05/msg01747.html (9,391 bytes)


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