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[xfs-masters] Learn and Network -- www.SoCconference.com -- The 4th Int

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Subject: [xfs-masters] Learn and Network -- www.SoCconference.com -- The 4th International System-on-Chip (SoC) Conference and Exhibit, Nov 1 & 2, 2006
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Date: 16 Oct 2006 14:06:13 -0700
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The Most Innovative and A= ffordably Priced Chip Design Technology
Conferenceof the Year= 

Don't Miss Out!= 

Discounts for Students an= d IEEE/ACM Members = 

4th Internatio= nal System-on-Chip (SoC) 

= Conference &Exhibit 

= November 1 &2, 2006 -&n= bsp;Radisson Hotel Newport Beach= , California 

  Regist= er TODAY! [1]

For Conference Information &Registration, Please Visit: [2]
= www.SoCconference.com[3] 

L= eading-edge Companies, Universities, and Organizations will be presenting
th= eir latest System-on-Chip (SoC), ASIC, ASSP, FPGA, and Foundry
technologies = and products in this informative and exciting Conference
&Exhibit. 

Participating Companies &Organizati= ons (a partial list= ):  Fujitsu, 
Samsung,  Micron Technology,  Synplicity,  Son= ics,  Tensilica,  IBM, 
Intel,  Toshiba,  Cadence,&= nbsp; Infineon,  Altera, Broadcom,  Tohoku
University,  ARM, =  Texas Instruments,  Wireles= s Design &Development,  IQ
,  Jazz Semiconductor,  The Spirit Consortium,  Synopsys, &n= bsp;STMicro, 
CISCO Systems,  Ambric,  Connex,   &n= bsp;LogicVision,  Innovative Silicon,
 Pacific Northwest National = Laboratory,  EMA Design Automation,  EuroAsia
Semiconductor= ,  National Semiconductor,  CMP,  Silistix,  ViASIC,&nb= sp;
CSU Fullerton, UC Irvine,  Magma,  Nascentric, First Sili= con,  EETimes ,
T=aylor &Francis - CRC Press,  San Jose State University,  Sili= con Hive, 
EDN , = CoWare,  RWTH Aachen University,   MEMS Manufacturing,  MPEG Forum, 
OCP-IP, = Circuit Cel= lar ,  Virage Logic,  DSP &FPGA,  Adaptive Labs, 
Sequ= ence Design,  Takumi Technology, CSU Long Beach,  AeA,  Savan= t
Company Inc.,  Chapman University,  Target Compiler Technologies= ,  IEEE
OC, VaST Systems Technology,  PalmChip,  EEMBC,=   Platinum Associates,
Advanced P= ackaging,  Semico= nductor Online ,  Embedded Computing ,  Ope=
nSystems Initiatives,  OCBC,  VSIA Alliance,  and many more.= =   

 Five Informative Tracks 
  * New CP= U and DSP Cores for Complex SoC Applications 
    * Networ= k-on-Chip (NoC) Architectures for Complex SoCs 
    * Memory= sub-system Advances and Trends 
    * Semico= nductor Trends and New Design Approaches for Complex SoCs = 
    * EDA To= ols and Design Methodologies for Complex SoCs = 


Five Outstand= ing Keynote Speakers 
  * Dr. Dominik Schmidt, &Arup Gupta, Intel.  &= nbsp; 
    * Dr. Juan-Antonio Carballo, IBM. 
    * Dr. Tadao Nakamura, Tohoku University, Japan. 
    * Ana Molnar Hunter, VP of Technology, Samsung. 
    * Dr. Mehdi Hatamian, VP of Engineering, Broadcom. 


Two Challengi= ng Panel Discussions 
  * Archit= ectural and Performance-Related Challenges for Complex SoCs. 
Moderator= : Ron Wilson, Executive Editor, EDN Worldwide. 
    * EDA Ch= allenges for Complex SoC and ASIC Designs. Moderator: Dave
Bursky, Semicondu= ctor Editor, EETimes Magazine. 


One Night of Tabletop Exhibitions (November = 1, 2006, 4:30 PM - 8:30 PM) 
  * Sign u= p online for complimentary exhibition passes (for November 1,
2006, Exhibiti= on night only). 
    * Meet o= ne-on-one with SoC experts representing a wide variety of
companies 
    * Have y= our toughest questions answered by leading-edge companies! 
    * Discus= s development tools and chip design challenges with
SoC/ASIC/Foundry experts= 
    * Connec= t with companies offering practical solutions to your design
challenges 
    * "Seein= g Is Believing!" See demos of EDA tools from leading-edge EDA
vendors 


Why You Should Attend 
  * Discus= s 65nm and post-65nm challenges for SoC/ASIC/ASSP/FPGA designs= 
    * Learn = about the latest configurable CPUs, Processors, and DSPs cores

    * Gain i= nsight into memory subsystems design for complex
SoC/ASIC/ASSP/FPGA designs 
    * Learn = about the new trends and future direction of System-on-Chip 
    * Networ= k with the leaders driving SoC technology during the
conference&exhibi= t = 
    * Learn about the latest EDA Tools and design techniques for Nanomete= r
SoCs 


Who Should Attend= 
  * Chip d= esigners = 
    * Design= engineers 
    * ASIC/S= oC/ASSP/FPGA designers 
    * EDA De= velopers 
    * System= architects 
    * IP Dev= elopers   
    * Hardwa= re engineers 
    * System= platform designers 
    * Execut= ives and business decision-makers in technology companies 
    * Techni= cal  marketing/sales professionals 
    * Techno= logy and business analysts 
    * Engine= ering professors and students 
    * Anyone= involved with ASIC, SoC, ASSP, Foundry, and FPGA design,
development, plann= ing, promotion, and procurement 


The 4th International System-on-Chip (SoC) Conference &Exhibit is the y=
ear's most important, most informative technical conference for the chip
des=ign community.  In collaboration with major industry enablers and top a=
cademic experts, it addresses the latest technologies and products from
vend=ors in semiconductor, EDA, IP, CPUs/DSPs, Memories, NoC, Multi-core,
etc. 

Discount for Students and IEEE &ACM Members 

  

The Most Informative and Targeted SoC &ASIC Conference &= amp; Exhibit[4] 

Event of the Year! [5]  

Don't Miss Out! 

Register Today!     http= ://www.SoCconference.com/[6] 

Please share this message with interested colleagues! 

Got a registration question? 
= Please email:  SoC@xxxxxxxxxxxxxxxxx[7]= 
&n= bsp; 

www.SoCconference.com[8] 





  

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"Remove" in the subjec= t line. 

Copyright ? 2005 by Savant Company Inc. PO Box 51330, Irvine, CA 92619,
U.S.A. All rights reserved. All names contained herein a= re the trademarks
of their respective holders. 

&= nbsp; 

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   5 3D"=
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