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[xfs-masters] Oct 9 - Deadline for Early Bird Registration--The 4th Inte

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Subject: [xfs-masters] Oct 9 - Deadline for Early Bird Registration--The 4th International System-on-Chip (SoC) Conference and Exhibit www.SoCconference.com
From: "SoC Conference" <SoC_Conf@xxxxxxxxxxxxxxxxx>
Date: Sun, 8 Oct 2006 18:13:49 -0700
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The Most Innovative and Affordably Priced Chip Design Technology Conference
of the Year

Don't Miss Out!

Special Discounts for Students and IEEE/ACM Members

 





4th International System-on-Chip (SoC)

Conference & Exhibit

November 1 & 2, 2006 - Radisson Hotel Newport Beach, California 

 

 <http://www.socconference.com/> Register TODAY & Save! 

 <http://www.socconference.com/> For Conference Information & Early Bird
Registration, Please Visit: 
 <http://www.socconference.com/> www.SoCconference.com 

Leading-edge Companies, Universities, and Organizations will be presenting
their latest System-on-Chip (SoC), ASIC, ASSP, FPGA, and Foundry
technologies and products in this informative and exciting Conference &
Exhibit. 

Participating Companies & Organizations (a partial list):  Fujitsu,
Samsung,  Micron Technology,  Synplicity,  Sonics,  Tensilica,  IBM,  Intel,
Toshiba,  Cadence,  Altera,  Broadcom, Infineon,  Tohoku University,  ARM,
Texas Instruments,  Wireless Design & Development,  IQ ,  Mentor Graphics, ,
Jazz Semiconductor,  The Spirit Consortium,  Synopsys,  STMicro,  CISCO
Systems, Ambric,  Connex,   LogicVision,  Innovative Silicon,  Pacific
Northwest National Laboratory,  EMA Design Automation,  EuroAsia
Semiconductor,  National Semiconductor,  CMP,  Silistix,  ViASIC,  CSU
Fullerton, UC Irvine,  Magma,  Nascentric, First Silicon,  EETimes , Taylor
& Francis - CRC Press,  San Jose State University,  Silicon Hive,  EDN ,
CoWare,  RWTH Aachen University,  MEMS Manufacturing,  MPEG Forum,  OCP-IP,
Circuit Cellar ,  Virage Logic,  DSP & FPGA,  Adaptive Labs,  Sequence
Design,  Takumi Technology, CSU Long Beach,  AeA,  Savant Company Inc.,
Chapman University,  Target Compiler Technologies,  IEEE OC,  VaST Systems
Technology,  PalmChip,  EEMBC,  Platinum Associates, Advanced Packaging,
Semiconductor Online ,  Embedded Computing ,  Open Systems Initiatives,
OCBC,  VSIA Alliance,  and many more.   

 

Five Informative Tracks

*       New CPU and DSP Cores for Complex SoC Applications 
*       Network-on-Chip (NoC) Architectures for Complex SoCs 
*       Memory sub-system Advances and Trends 
*       Semiconductor Trends and New Design Approaches for Complex SoCs 
*       EDA Tools and Design Methodologies for Complex SoCs

Five Outstanding Keynote Speakers 

*       Dr. Dominik Schmidt, & Arup Gupta, Intel.    
*       Dr. Juan-Antonio Carballo, IBM. 
*       Dr. Tadao Nakamura, Tohoku University, Japan. 
*       Ana Molnar Hunter, VP of Technology, Samsung. 
*       Dr. Mehdi Hatamian, VP of Engineering, Broadcom. 

Two Challenging Panel Discussions 

*       Architectural and Performance-Related Challenges for Complex SoCs.
Moderator: Ron Wilson, Executive Editor, EDN Worldwide. 
*       EDA Challenges for Complex SoC and ASIC Designs. Moderator: Dave
Bursky, Semiconductor Editor, EETimes Magazine. 

One Night of Tabletop Exhibitions (November 1, 2006, 4:30 PM - 8:30 PM) 

*       Sign up online for complimentary exhibition passes (for November 1,
2006, Exhibition night only). 
*       Meet one-on-one with SoC experts representing a wide variety of
companies 
*       Have your toughest questions answered by leading-edge companies! 
*       Discuss development tools and chip design challenges with
SoC/ASIC/Foundry experts 
*       Connect with companies offering practical solutions to your design
challenges 
*       "Seeing Is Believing!" See demos of EDA tools from leading-edge EDA
vendors

Why You Should Attend

*       Discuss 65nm and post-65nm challenges for SoC/ASIC/ASSP/FPGA designs

*       Learn about the latest configurable CPUs, Processors, and DSPs cores

*       Gain insight into memory subsystems design for complex
SoC/ASIC/ASSP/FPGA designs 
*       Learn about the new trends and future direction of System-on-Chip 
*       Network with the leaders driving SoC technology during the
conference & exhibit 
*       Learn about the latest EDA Tools and design techniques for Nanometer
SoCs

Who Should Attend 

*       Chip designers 
*       Design engineers 
*       ASIC/SoC/ASSP/FPGA designers 
*       EDA Developers 
*       System architects 
*       IP Developers   
*       Hardware engineers 
*       System platform designers 
*       Executives and business decision-makers in technology companies 
*       Technical  marketing/sales professionals 
*       Technology and business analysts 
*       Engineering professors and students 
*       Anyone involved with ASIC, SoC, ASSP, Foundry, and FPGA design,
development, planning, promotion, and procurement

The 4th International System-on-Chip (SoC) Conference & Exhibit is the
year's most important, most informative technical conference for the chip
design community.  In collaboration with major industry enablers and top
academic experts, it addresses the latest technologies and products from
vendors in semiconductor, EDA, IP, CPUs/DSPs, Memories, NoC, Multi-core,
etc. 

Special Discount for Students and IEEE & ACM Members

 

 <http://www.savantcompany.com/SoC4-Fall2006/main.htm> The Most Informative
and Targeted SoC & ASIC Conference & Exhibit

 <http://www.savantcompany.com/SoC4-Fall2006/main.htm> Event of the Year!  

Don't Miss Out! 

Register Today and Save!     <http://www.socconference.com/>
http://www.SoCconference.com/

Please share this message with interested colleagues!

Got a registration question? 
Please email:   <mailto:SoC@xxxxxxxxxxxxxxxxx> SoC@xxxxxxxxxxxxxxxxx 
 

 

 <http://www.socconference.com/> www.SoCconference.com

 

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SoC-News@xxxxxxxxxxxxxxxxx with "Remove" in the subject line. 

Copyright ? 2005 by Savant Company Inc. PO Box 51330, Irvine, CA 92619,
U.S.A. All rights reserved. All names contained herein are the trademarks of
their respective holders.

 

 



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