| To: | Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: [PATCH] use mmiowb in tg3.c |
| From: | <akepner@xxxxxxx> |
| Date: | Thu, 21 Oct 2004 18:33:22 -0700 (PDT) |
| Cc: | "David S. Miller" <davem@xxxxxxxxxxxxx>, Jesse Barnes <jbarnes@xxxxxxxxxxxx>, Andrew Morton <akpm@xxxxxxxx>, Linux Kernel list <linux-kernel@xxxxxxxxxxxxxxx>, <netdev@xxxxxxxxxxx>, Jeff Garzik <jgarzik@xxxxxxxxx>, <gnb@xxxxxxx> |
| In-reply-to: | <1098407804.6071.22.camel@gaston> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
On Fri, 22 Oct 2004, Benjamin Herrenschmidt wrote: > ... > Typically, our normal "light" write barrier doesn't reorder between cacheable > and non-cacheable (MMIO) stores, which is why we had to put some heavy sync > barrier in our MMIO writes macros. > ... Do you mean "impose order" rather than "reorder" here? -- Arthur |
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