| To: | "David S. Miller" <davem@xxxxxxxxxxxxx>, raghavendra.koushik@xxxxxxxxxxxx |
|---|---|
| Subject: | Re: [PATCH 2.6.12.1 5/12] S2io: Performance improvements |
| From: | Jeff Garzik <jgarzik@xxxxxxxxx> |
| Date: | Thu, 07 Jul 2005 23:08:02 -0400 |
| Cc: | akepner@xxxxxxx, netdev@xxxxxxxxxxx, netdev@xxxxxxxxxxxxxxx, ravinandan.arakali@xxxxxxxxxxxx, leonid.grossman@xxxxxxxxxxxx, rapuru.sriram@xxxxxxxxxxxx |
| In-reply-to: | <20050707.200034.74747399.davem@davemloft.net> |
| References: | <Pine.LNX.4.61.0507071552130.24321@resonance.WorkGroup> <200507080106.j6816NKP022996@guinness.s2io.com> <20050707.200034.74747399.davem@davemloft.net> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
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David S. Miller wrote:
If you need a PIO to complete in a specific order, you have to read it back. If you need PIO operations to occur
A PCI read is the only way to ensure that all the CPU/PCI bridge buffers are flushed to the device. Whenever Arjan and I complain about "PCI posting" problems, we are indicating a need for additional readl() calls to ensure ordering/flushing. Delaying immediately after a writel() is a classic PCI posting mistake. Assuming ordering is another. Jeff |
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