| To: | Michael Chan <mchan@xxxxxxxxxxxx> |
|---|---|
| Subject: | Re: [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt |
| From: | Jeff Garzik <jgarzik@xxxxxxxxx> |
| Date: | Tue, 22 Mar 2005 15:53:29 -0500 |
| Cc: | "David S. Miller" <davem@xxxxxxxxxxxxx>, netdev@xxxxxxxxxxx |
| In-reply-to: | <B1508D50A0692F42B217C22C02D84972020F3E22@NT-IRVA-0741.brcm.ad.broadcom.com> |
| References: | <B1508D50A0692F42B217C22C02D84972020F3E22@NT-IRVA-0741.brcm.ad.broadcom.com> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| User-agent: | Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.3) Gecko/20040922 |
Michael Chan wrote:
Add register read of PCI state register in tg3_interrupt() if status block's updated bit is not set. This will flush the status block and confirm whether the interrupt is ours or not. PCI ordering rules allow the interrupt to arrive at the CPU ahead of the status block that may be posted at the chipset.
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