| To: | "Michael Chan" <mchan@xxxxxxxxxxxx> |
|---|---|
| Subject: | Re: [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750 |
| From: | "David S. Miller" <davem@xxxxxxxxxxxxx> |
| Date: | Wed, 23 Mar 2005 11:09:18 -0800 |
| Cc: | netdev@xxxxxxxxxxx |
| In-reply-to: | <B1508D50A0692F42B217C22C02D84972020F3E25@NT-IRVA-0741.brcm.ad.broadcom.com> |
| References: | <B1508D50A0692F42B217C22C02D84972020F3E25@NT-IRVA-0741.brcm.ad.broadcom.com> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
On Sun, 20 Mar 2005 23:48:13 -0800 "Michael Chan" <mchan@xxxxxxxxxxxx> wrote: > Add unstable PLL clock workaround for 5750 Ax and Bx devices. The workaround > code is run just before entering D3hot state. > > Signed-off-by: Michael Chan <mchan@xxxxxxxxxxxx> Applied, thanks Michael. |
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