| To: | Andi Kleen <ak@xxxxxx> |
|---|---|
| Subject: | Re: Intel and TOE in the news |
| From: | Lennert Buytenhek <buytenh@xxxxxxxxxxxxxx> |
| Date: | Sat, 19 Feb 2005 21:32:04 +0100 |
| Cc: | "David S. Miller" <davem@xxxxxxxxxxxxx>, jgarzik@xxxxxxxxx, netdev@xxxxxxxxxxx |
| In-reply-to: | <m1psywb8i4.fsf@muc.de> |
| References: | <4216B62D.6000502@pobox.com> <20050219041007.GA17896@xi.wantstofly.org> <20050219114624.373af63f.davem@davemloft.net> <m1psywb8i4.fsf@muc.de> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| User-agent: | Mutt/1.4.1i |
On Sat, Feb 19, 2005 at 09:27:31PM +0100, Andi Kleen wrote: > It would be nice if the NIC could asynchronously trigger prefetches > in the CPU. Currently a lot of the packet processing cost goes to > waiting for read cache misses. I've been told that this is something that the BCM-1250 can do. The MACs are in the CPU, and they can (reportedly) DMA the packet headers straight into L2. --L |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: Intel and TOE in the news, Lennert Buytenhek |
|---|---|
| Next by Date: | Re: [PATCH 2/3] r8169: code clean-up, Francois Romieu |
| Previous by Thread: | Re: Intel and TOE in the news, Andi Kleen |
| Next by Thread: | Re: Intel and TOE in the news, Eugene Surovegin |
| Indexes: | [Date] [Thread] [Top] [All Lists] |