| To: | Evgeniy Polyakov <johnpol@xxxxxxxxxxx> |
|---|---|
| Subject: | Re: Asynchronous crypto layer. |
| From: | Eugene Surovegin <ebs@xxxxxxxxxxx> |
| Date: | Sat, 30 Oct 2004 13:35:50 -0700 |
| Cc: | hadi@xxxxxxxxxx, netdev@xxxxxxxxxxx, cryptoapi@xxxxxxxxxxxxxx |
| In-reply-to: | <20041029180652.113f0f6e@zanzibar.2ka.mipt.ru> |
| Mail-followup-to: | Evgeniy Polyakov <johnpol@xxxxxxxxxxx>, hadi@xxxxxxxxxx, netdev@xxxxxxxxxxx, cryptoapi@xxxxxxxxxxxxxx |
| References: | <1099030958.4944.148.camel@uganda> <1099053738.1024.104.camel@jzny.localdomain> <20041029180652.113f0f6e@zanzibar.2ka.mipt.ru> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| User-agent: | Mutt/1.5.5.1i |
On Fri, Oct 29, 2004 at 06:06:52PM +0400, Evgeniy Polyakov wrote: > If we have a hardware accelerator chip, than we _already_ have improvements > with even the worst async crypto layer, since software and hardware > will work in parrallel. This is not true. For example, if chip request setup and PCI transfer takes more than just using sw implementation. This is reality for AES and short packets. -- Eugene |
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