| To: | Harald Welte <laforge@xxxxxxxxxxxx> |
|---|---|
| Subject: | Re: recommendations for NIC HW(/SW) design? |
| From: | Lennert Buytenhek <buytenh@xxxxxxxxxxxxxx> |
| Date: | Tue, 28 Sep 2004 10:12:42 +0200 |
| Cc: | netdev@xxxxxxxxxxx |
| In-reply-to: | <20040927155144.GU3236@sunbeam.de.gnumonks.org> |
| References: | <20040926152955.GD17043@xi.wantstofly.org> <20040927155144.GU3236@sunbeam.de.gnumonks.org> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| User-agent: | Mutt/1.4.1i |
On Mon, Sep 27, 2004 at 05:51:44PM +0200, Harald Welte wrote: > > (Since the Intel IXP processor is just an ARM processor with a network > > interface grafted onto the chip, a bunch of things that apply to PCI > > NIC design might not apply here.) > > I think this IXP is only a UP architecture, is it? Yeah, it's a single-core ARM with a big fat pipe (either 4 or 10 Gb/s depending on model) grafted onto the CPU. --L |
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