On Sun, Sep 26, 2004 at 05:29:55PM +0200, Lennert Buytenhek wrote:
> (Since the Intel IXP processor is just an ARM processor with a network
> interface grafted onto the chip, a bunch of things that apply to PCI
> NIC design might not apply here.)
I think this IXP is only a UP architecture, is it? For SMP scalability
it would be nice to specify the Tx Interrupt in every descriptor, so you
can cause Tx interrupts go to the cpu that actually sent the packet
(cache locality).
> thanks,
> Lennert
--
- Harald Welte <laforge@xxxxxxxxxxxx> http://www.gnumonks.org/
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