| To: | Lennert Buytenhek <buytenh@xxxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: recommendations for NIC HW(/SW) design? |
| From: | "David S. Miller" <davem@xxxxxxxxxxxxx> |
| Date: | Sun, 26 Sep 2004 20:53:04 -0700 |
| Cc: | netdev@xxxxxxxxxxx |
| In-reply-to: | <20040926152955.GD17043@xi.wantstofly.org> |
| References: | <20040926152955.GD17043@xi.wantstofly.org> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
On Sun, 26 Sep 2004 17:29:55 +0200 Lennert Buytenhek <buytenh@xxxxxxxxxxxxxx> wrote: > Does any of you have any general recommendations for this? Is there > anything I should certainly implement, or any design mistakes that I > should certainly avoid? The best thing I think the tg3 does is that it uses 3 rings for packet management. There is one transmit ring, one receive ring, and "response" ring. The cpu only writes to the first two rings, and the chip only writes to the third ring. And this is great for cache behavior on the bus. |
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