Re: fealnx oopses

[Denis Vlasenko <vda@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>]

On Saturday 27 March 2004 00:35, Francois Romieu wrote:
> Denis Vlasenko <vda@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> :
> [...]
>
> > Yes. But on x86 a++ is atomic vs interrupts - it's a single instruction
> > and interrupts happen on instruction boundaries only.
>
> Do you realize that you are saying that the CPU can atomically increment an
> integer which sits _in memory_ ?

Not exactly. CPU does not atomically increment memory.
I am saying that x86 CPU can't be interrupted in the middle
of read-modify-write operation, like

                incl    (%eax)

because it is single machine instruction. Interrupt either
happens before it, and handler see 'old' value, or after it,
and handler see 'new' value. Interrupt cannot happen 'inside' it.

Some RISC processors lack such single-instruction RMW ops.
Bug can thrigger on those CPUs:
                load    (%r1),r2
                inc     v2      
                        <-------- interrupt here. Ouch!
                store   v2,(%r1)
Not on x86.
--
vda