| To: | kumarkr@xxxxxxxxxx |
|---|---|
| Subject: | Re: [PATCH]snmp6 64-bit counter support in proc.c |
| From: | "David S. Miller" <davem@xxxxxxxxxx> |
| Date: | Thu, 22 Jan 2004 16:35:04 -0800 (PST) |
| Cc: | kuznet@xxxxxxxxxxxxx, mashirle@xxxxxxxxxx, netdev@xxxxxxxxxxx, xma@xxxxxxxxxx |
| In-reply-to: | <OFA2457112.0F3CBC9D-ON88256E23.007C851A@us.ibm.com> |
| References: | <OFA2457112.0F3CBC9D-ON88256E23.007C851A@us.ibm.com> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
From: Krishna Kumar <kumarkr@xxxxxxxxxx> Date: Thu, 22 Jan 2004 14:50:15 -0800 Isn't memory barrier used to stop re-ordering of instructions and needs to be present in both reader as well as writer to have synchronization since mb is for the CPU on which it is executing ? You are correct. Good thing I delayed this for a release, now we can work on making sure we get this right. :-) |
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