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Re: TOE brain dump

To: Werner Almesberger <werner@xxxxxxxxxxxxxxx>
Subject: Re: TOE brain dump
From: "David S. Miller" <davem@xxxxxxxxxx>
Date: Mon, 4 Aug 2003 12:26:32 -0700
Cc: ebiederm@xxxxxxxxxxxx, jgarzik@xxxxxxxxx, niv@xxxxxxxxxx, netdev@xxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx
In-reply-to: <20030804162433.L5798@almesberger.net>
References: <20030802140444.E5798@almesberger.net> <3F2BF5C7.90400@us.ibm.com> <3F2C0C44.6020002@pobox.com> <20030802184901.G5798@almesberger.net> <m1fzkiwnru.fsf@frodo.biederman.org> <20030804162433.L5798@almesberger.net>
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On Mon, 4 Aug 2003 16:24:33 -0300
Werner Almesberger <werner@xxxxxxxxxxxxxxx> wrote:

> Eric W. Biederman wrote:
> > There is one place in low latency communications that I can think
> > of where TCP/IP is not the proper solution.  For low latency
> > communication the checksum is at the wrong end of the packet.
> 
> That's one of the few things ATM's AAL5 got right.

Let's recall how long the IFF_TRAILERS hack from BSD :-)

> But in the end, I think it doesn't really matter.

I tend to agree on this one.

And on the transmit side if you have more than 1 pending TX frame, you
can always be prefetching the next one into the fifo so that by the
time the medium is ready all the checksum bits have been done.

In fact I'd be surprised if current generation 1g/10g cards are not
doing something like this.

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