| To: | ebiederm@xxxxxxxxxxxx |
|---|---|
| Subject: | Re: Info: NAPI performance at "low" loads |
| From: | "David S. Miller" <davem@xxxxxxxxxx> |
| Date: | Wed, 18 Sep 2002 13:23:34 -0700 (PDT) |
| Cc: | hadi@xxxxxxxxxx, akpm@xxxxxxxxx, manfred@xxxxxxxxxxxxxxxx, netdev@xxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx |
| In-reply-to: | <m1hegnky2h.fsf@frodo.biederman.org> |
| References: | <Pine.GSO.4.30.0209172053360.3686-100000@shell.cyberus.ca> <20020917.180014.07882539.davem@redhat.com> <m1hegnky2h.fsf@frodo.biederman.org> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
From: ebiederm@xxxxxxxxxxxx (Eric W. Biederman)
Date: 18 Sep 2002 11:27:34 -0600
"David S. Miller" <davem@xxxxxxxxxx> writes:
> {in,out}{b,w,l}() operations have a fixed timing, therefore his
> results doesn't sound that far off.
????
I don't see why they should be. If it is a pci device the cost should
the same as a pci memory I/O. The bus packets are the same. So things like
increasing the pci bus speed should make it take less time.
The x86 processor has a well defined timing for executing inb
etc. instructions, the timing is fixed and is independant of the
speed of the PCI bus the device is on.
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