| To: | Grant Grundler <grundler@xxxxxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: Linux support for RDMA (was: [Ksummit-2005-discuss] Summary of 2005 Kernel Summit Proposed Topics) |
| From: | Dmitry Yusupov <dmitry_yus@xxxxxxxxx> |
| Date: | Mon, 04 Apr 2005 09:54:10 -0700 |
| Cc: | "open-iscsi@xxxxxxxxxxxxxxxx" <open-iscsi@xxxxxxxxxxxxxxxx>, "David S. Miller" <davem@xxxxxxxxxxxxx>, mpm@xxxxxxxxxxx, andrea@xxxxxxx, michaelc@xxxxxxxxxxx, James.Bottomley@xxxxxxxxxxxxxxxxxxxxx, ksummit-2005-discuss@xxxxxxxxx, netdev@xxxxxxxxxxx |
| In-reply-to: | <20050404063456.GB30855@colo.lackof.org> |
| References: | <67D69596DDF0C2448DB0F0547D0F947E01781F2E@yogi.asicdesigners.com> <1112576171.4227.5.camel@mylaptop> <20050404063456.GB30855@colo.lackof.org> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
On Mon, 2005-04-04 at 00:34 -0600, Grant Grundler wrote: > On Sun, Apr 03, 2005 at 05:56:11PM -0700, Dmitry Yusupov wrote: > > I do not get your concern with memory BW. With good AMD box V40Z(SUN) > > you can get 5.3GBytes/sec. Even with 10Gbps full speed you have 80% > > left. PCI-X BUS BW is bigger concern... > > Yes and No. PCI-X isn't fast enough but the data only crosses > the PCI-X bus once. Think about the data flow: > 1) DMA to RAM yes. > 2) load into CPU cache yes. > 3) store back into RAM no. we are talking about receive side optimization only. why do you think store back into RAM comes to the picture? also keep in mind that we have huge L2 & L3 caches today and write operation is usually very well buffered. > We are down to 40% left...graphics folks won't like you. > > grant > |
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