| To: | "David S. Miller" <davem@xxxxxxxxxx> |
|---|---|
| Subject: | Re: Info: NAPI performance at "low" loads |
| From: | Alan Cox <alan@xxxxxxxxxxxxxxxxxxx> |
| Date: | 18 Sep 2002 21:43:09 +0100 |
| Cc: | ebiederm@xxxxxxxxxxxx, hadi@xxxxxxxxxx, akpm@xxxxxxxxx, manfred@xxxxxxxxxxxxxxxx, netdev@xxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx |
| In-reply-to: | <20020918.132334.102949210.davem@redhat.com> |
| References: | <Pine.GSO.4.30.0209172053360.3686-100000@shell.cyberus.ca> <20020917.180014.07882539.davem@redhat.com> <m1hegnky2h.fsf@frodo.biederman.org> <20020918.132334.102949210.davem@redhat.com> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
On Wed, 2002-09-18 at 21:23, David S. Miller wrote: > The x86 processor has a well defined timing for executing inb > etc. instructions, the timing is fixed and is independant of the > speed of the PCI bus the device is on. Earth calling Dave Miller The inb timing depends on the PCI bus. If you want proof set a Matrox G400 into no pci retry mode, run a large X load at it and time some inbs you should be able to get to about 100 milliseconds for an inb to execute |
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