Return to iop_trigger_grp_defs_asm.h CVS log

Up to [Development] / linux-2.6-xfs / include / asm-cris / arch-v32 / hwregs / iop / asm

Update 2.6.x-xfs to 2.6.23-rc4.

Also update fs/xfs with external mainline changes.
There were 12 such missing commits that I detected:

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commit ad690ef9e690f6c31f7d310b09ef1314bcec9033
Author: Al Viro <viro@ftp.linux.org.uk>
    xfs ioctl __user annotations

commit 20c2df83d25c6a95affe6157a4c9cac4cf5ffaac
Author: Paul Mundt <lethal@linux-sh.org>
    mm: Remove slab destructors from kmem_cache_create().

commit d0217ac04ca6591841e5665f518e38064f4e65bd
Author: Nick Piggin <npiggin@suse.de>
    mm: fault feedback #1

commit 54cb8821de07f2ffcd28c380ce9b93d5784b40d7
Author: Nick Piggin <npiggin@suse.de>
    mm: merge populate and nopage into fault (fixes nonlinear)

commit d00806b183152af6d24f46f0c33f14162ca1262a
Author: Nick Piggin <npiggin@suse.de>
    mm: fix fault vs invalidate race for linear mappings

commit a569425512253992cc64ebf8b6d00a62f986db3e
Author: Christoph Hellwig <hch@infradead.org>
    knfsd: exportfs: add exportfs.h header

commit 831441862956fffa17b9801db37e6ea1650b0f69
Author: Rafael J. Wysocki <rjw@sisk.pl>
    Freezer: make kernel threads nonfreezable by default

commit 8e1f936b73150f5095448a0fee6d4f30a1f9001d
Author: Rusty Russell <rusty@rustcorp.com.au>
    mm: clean up and kernelify shrinker registration

commit 5ffc4ef45b3b0a57872f631b4e4ceb8ace0d7496
Author: Jens Axboe <jens.axboe@oracle.com>
    sendfile: remove .sendfile from filesystems that use generic_file_sendfile()

commit 8bb7844286fb8c9fce6f65d8288aeb09d03a5e0d
Author: Rafael J. Wysocki <rjw@sisk.pl>
    Add suspend-related notifications for CPU hotplug

commit 59c51591a0ac7568824f541f57de967e88adaa07
Author: Michael Opdenacker <michael@free-electrons.com>
    Fix occurrences of "the the "

commit 0ceb331433e8aad9c5f441a965d7c681f8b9046f
Author: Dmitriy Monakhov <dmonakhov@openvz.org>
    mm: move common segment checks to separate helper function
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Merge of 2.6.x-xfs-melb:linux:29656b by kenmcd.

#ifndef __iop_trigger_grp_defs_asm_h
#define __iop_trigger_grp_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
 *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
 *     last modfied: Mon Apr 11 16:08:46 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
 *      id: $Id: iop_trigger_grp_defs_asm.h,v 1.13 2007/09/12 17:09:56 tes.longdrop.melbourne.sgi.com Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

#define STRIDE_iop_trigger_grp_rw_cfg 4
/* Register rw_cfg, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
#define reg_iop_trigger_grp_rw_cfg___action___width 2
#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
#define reg_iop_trigger_grp_rw_cfg___once___width 1
#define reg_iop_trigger_grp_rw_cfg___once___bit 2
#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
#define reg_iop_trigger_grp_rw_cfg___trig___width 3
#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
#define reg_iop_trigger_grp_rw_cfg_offset 0

/* Register rw_cmd, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
#define reg_iop_trigger_grp_rw_cmd___dis___width 4
#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
#define reg_iop_trigger_grp_rw_cmd___en___width 4
#define reg_iop_trigger_grp_rw_cmd_offset 16

/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
#define reg_iop_trigger_grp_rw_intr_mask_offset 20

/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
#define reg_iop_trigger_grp_rw_ack_intr_offset 24

/* Register r_intr, scope iop_trigger_grp, type r */
#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
#define reg_iop_trigger_grp_r_intr___trig0___width 1
#define reg_iop_trigger_grp_r_intr___trig0___bit 0
#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
#define reg_iop_trigger_grp_r_intr___trig1___width 1
#define reg_iop_trigger_grp_r_intr___trig1___bit 1
#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
#define reg_iop_trigger_grp_r_intr___trig2___width 1
#define reg_iop_trigger_grp_r_intr___trig2___bit 2
#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
#define reg_iop_trigger_grp_r_intr___trig3___width 1
#define reg_iop_trigger_grp_r_intr___trig3___bit 3
#define reg_iop_trigger_grp_r_intr_offset 28

/* Register r_masked_intr, scope iop_trigger_grp, type r */
#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
#define reg_iop_trigger_grp_r_masked_intr_offset 32


/* Constants */
#define regk_iop_trigger_grp_fall                 0x00000002
#define regk_iop_trigger_grp_fall_lo              0x00000006
#define regk_iop_trigger_grp_no                   0x00000000
#define regk_iop_trigger_grp_off                  0x00000000
#define regk_iop_trigger_grp_pulse                0x00000000
#define regk_iop_trigger_grp_rise                 0x00000001
#define regk_iop_trigger_grp_rise_fall            0x00000003
#define regk_iop_trigger_grp_rise_fall_hi         0x00000007
#define regk_iop_trigger_grp_rise_fall_lo         0x00000004
#define regk_iop_trigger_grp_rise_hi              0x00000005
#define regk_iop_trigger_grp_rw_cfg_default       0x000000c0
#define regk_iop_trigger_grp_rw_cfg_size          0x00000004
#define regk_iop_trigger_grp_rw_intr_mask_default  0x00000000
#define regk_iop_trigger_grp_toggle               0x00000003
#define regk_iop_trigger_grp_yes                  0x00000001
#endif /* __iop_trigger_grp_defs_asm_h */