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| File: [Development] / linux-2.6-xfs / arch / i386 / kernel / acpi / Attic / cstate.c (download)
Revision 1.2, Mon Feb 6 14:53:10 2006 UTC (11 years, 8 months ago) by nathans.longdrop.melbourne.sgi.com
Merge up to 2.6.16-rc2. Merge of 2.6.x-xfs-melb:linux:25118a by kenmcd. |
/*
* arch/i386/kernel/acpi/cstate.c
*
* Copyright (C) 2005 Intel Corporation
* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
* - Added _PDC for SMP C-states on Intel CPUs
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <acpi/processor.h>
#include <asm/acpi.h>
/*
* Initialize bm_flags based on the CPU cache properties
* On SMP it depends on cache configuration
* - When cache is not shared among all CPUs, we flush cache
* before entering C3.
* - When cache is shared among all CPUs, we use bm_check
* mechanism as in UP case
*
* This routine is called only after all the CPUs are online
*/
void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
unsigned int cpu)
{
struct cpuinfo_x86 *c = cpu_data + cpu;
flags->bm_check = 0;
if (num_online_cpus() == 1)
flags->bm_check = 1;
else if (c->x86_vendor == X86_VENDOR_INTEL) {
/*
* Today all CPUs that support C3 share cache.
* TBD: This needs to look at cache shared map, once
* multi-core detection patch makes to the base.
*/
flags->bm_check = 1;
}
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);