Return to dram_init.S CVS log

Up to [Development] / linux-2.6-xfs / arch / cris / arch-v32 / lib

Update 2.6.x-xfs to 2.6.23-rc4.

Also update fs/xfs with external mainline changes.
There were 12 such missing commits that I detected:

--------
commit ad690ef9e690f6c31f7d310b09ef1314bcec9033
Author: Al Viro <viro@ftp.linux.org.uk>
    xfs ioctl __user annotations

commit 20c2df83d25c6a95affe6157a4c9cac4cf5ffaac
Author: Paul Mundt <lethal@linux-sh.org>
    mm: Remove slab destructors from kmem_cache_create().

commit d0217ac04ca6591841e5665f518e38064f4e65bd
Author: Nick Piggin <npiggin@suse.de>
    mm: fault feedback #1

commit 54cb8821de07f2ffcd28c380ce9b93d5784b40d7
Author: Nick Piggin <npiggin@suse.de>
    mm: merge populate and nopage into fault (fixes nonlinear)

commit d00806b183152af6d24f46f0c33f14162ca1262a
Author: Nick Piggin <npiggin@suse.de>
    mm: fix fault vs invalidate race for linear mappings

commit a569425512253992cc64ebf8b6d00a62f986db3e
Author: Christoph Hellwig <hch@infradead.org>
    knfsd: exportfs: add exportfs.h header

commit 831441862956fffa17b9801db37e6ea1650b0f69
Author: Rafael J. Wysocki <rjw@sisk.pl>
    Freezer: make kernel threads nonfreezable by default

commit 8e1f936b73150f5095448a0fee6d4f30a1f9001d
Author: Rusty Russell <rusty@rustcorp.com.au>
    mm: clean up and kernelify shrinker registration

commit 5ffc4ef45b3b0a57872f631b4e4ceb8ace0d7496
Author: Jens Axboe <jens.axboe@oracle.com>
    sendfile: remove .sendfile from filesystems that use generic_file_sendfile()

commit 8bb7844286fb8c9fce6f65d8288aeb09d03a5e0d
Author: Rafael J. Wysocki <rjw@sisk.pl>
    Add suspend-related notifications for CPU hotplug

commit 59c51591a0ac7568824f541f57de967e88adaa07
Author: Michael Opdenacker <michael@free-electrons.com>
    Fix occurrences of "the the "

commit 0ceb331433e8aad9c5f441a965d7c681f8b9046f
Author: Dmitriy Monakhov <dmonakhov@openvz.org>
    mm: move common segment checks to separate helper function
--------
Merge of 2.6.x-xfs-melb:linux:29656b by kenmcd.

/* $Id: dram_init.S,v 1.13 2007/09/12 17:09:56 tes.longdrop.melbourne.sgi.com Exp $
 *
 * DRAM/SDRAM initialization - alter with care
 * This file is intended to be included from other assembler files
 *
 * Note: This file may not modify r8 or r9 because they are used to
 * carry information from the decompresser to the kernel
 *
 * Copyright (C) 2000-2003 Axis Communications AB
 *
 * Authors:  Mikael Starvik (starvik@axis.com)
 */

/* Just to be certain the config file is included, we include it here
 * explicitely instead of depending on it being included in the file that
 * uses this code.
 */

#include <asm/arch/hwregs/asm/reg_map_asm.h>
#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>

	;; WARNING! The registers r8 and r9 are used as parameters carrying
	;; information from the decompressor (if the kernel was compressed).
	;; They should not be used in the code below.

	; Refer to BIF MDS for a description of SDRAM initialization

	; Bank configuration
	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
	move.d   $r1, [$r0]
	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
	move.d   CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
	move.d   $r1, [$r0]

	; Calculate value of mrs_data
	; CAS latency = 2 && bus_width = 32 => 0x40
	; CAS latency = 3 && bus_width = 32 => 0x60
	; CAS latency = 2 && bus_width = 16 => 0x20
	; CAS latency = 3 && bus_width = 16 => 0x30

	; Check if value is already supplied in kernel config
	move.d   CONFIG_ETRAX_SDRAM_COMMAND, $r2
	bne	 _set_timing
	nop

	move.d   0x40, $r4       ; Assume 32 bits and CAS latency = 2
	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
 	and.d    0x07, $r1       ; Get CAS latency
	cmpq	 2, $r1		 ; CL = 2 ?
	beq	 _bw_check
	nop
	move.d   0x60, $r4

_bw_check:
	; Assume that group 0 width is equal to group 1. This assumption
	; is wrong for a group 1 only hardware (such as the grand old
	; StorPoint+).
	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
	and.d    0x200, $r1	; DRAM width is bit 9
	beq      _set_timing
	lslq	 2, $r4		;  mrs_data starts at bit 2
	lsrq     1, $r4		;  16 bits. Shift down value.

	; Set timing parameters (refresh off to avoid Guinness TR 83)
_set_timing:
	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
	and.d    ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
	move.d   $r1, [$r0]

	; Issue NOP command
	move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
	moveq regk_bif_core_nop, $r1
	move.d $r1, [$r5]

	; Wait 200us
	move.d   10000, $r2
1:	bne      1b
	subq     1, $r2

	; Issue initialization command sequence
	move.d   _sdram_commands_start, $r2
	and.d    0x000fffff, $r2 ; Make sure commands are read from flash
	move.d   _sdram_commands_end,  $r3
	and.d    0x000fffff, $r3
1:	clear.d  $r6
	move.b   [$r2+], $r6 	; Load command
	or.d     $r4, $r6	; Add calculated mrs
	move.d   $r6, [$r5]	; Write rw_sdram_cmd
	; Wait 80 ns between each command
	move.d	 4000, $r7
2:	bne	 2b
	subq	 1, $r7
	cmp.d    $r2, $r3	; Last command?
	bne      1b
	nop

	; Start refresh
	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
	move.d   $r1, [$r0]

	; Initialization finished
	ba       _sdram_commands_end
	nop

_sdram_commands_start:
	.byte   regk_bif_core_pre ; Precharge
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_ref ; refresh
	.byte   regk_bif_core_mrs ; mrs
_sdram_commands_end: