Re: SGI linux from CVS crashes on boot

["Andi Kleen" <ak@xxxxxxx>]

On Mon, Apr 03, 2000 at 12:45:14PM -0400, Jim Bray wrote:
> 
>   According to the EIP, it is crashing in page_fault. EIP=c010af30,
> page_fault=c010af28. The sequence is
> 
> VFS: Mounted root (ext2 filesystem) readonly
> Freeing unused kernel memory: 148k freed
> General Protection Fault: 0000
> EIP=etcetc.
> 
> k6 box, debian/unstable system. Crash happens with or without xfs

It is KDB's fault. It uses Intel specific MSRs directly. They don't
exist on the K6 and it tells you that with a GPF. 

Apply the following patch. Steve, it seems the KDB patch didn't make it 
into the CVS tree yet.


-Andi

--- arch/i386/kernel/entry.S-o  Thu Mar 16 23:51:14 2000
+++ arch/i386/kernel/entry.S    Fri Mar 17 21:47:47 2000
@@ -432,6 +432,7 @@
        jmp error_code
 
 ENTRY(page_fault)
+#if 0
        pushl %ecx
        pushl %edx
        pushl %eax
@@ -442,6 +443,7 @@
        popl  %eax
        popl  %edx
        popl  %ecx
+#endif
        pushl $ SYMBOL_NAME(do_page_fault)
        jmp error_code
 
--- arch/i386/kdb/kdbasupport.c-o       Thu Mar 16 23:51:14 2000
+++ arch/i386/kdb/kdbasupport.c Fri Mar 17 20:59:27 2000
@@ -37,6 +37,40 @@
 unsigned long smp_kdb_wait;
 #endif
 
+enum cpu { IntelP5, IntelP6, AmdK6, Unknown } kdba_msrtype; 
+
+/* The normal kernel does the same, but be independent. */ 
+static void 
+checkcpu(void) 
+{ 
+       union { 
+               char str[12]; 
+               __u32 reg[3];  
+       } v; 
+       int eax,ebx,ecx,edx; 
+       __asm__("cpuid" 
+               : "=a" (eax), "=b" (v.reg[0]) , "=c" (v.reg[1]), "=d" (v.reg[2])
+               : "a" (0)); 
+       __asm__("cpuid"
+               : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+               : "a" (1)); 
+
+       kdba_msrtype = Unknown; 
+       if (!strcmp(v.str, "GenuineIntel")) {
+               switch ((ebx >> 4) & 0xF) { 
+               case 5:
+                       kdba_msrtype = IntelP5;
+                       break;
+               case 6:
+                       kdba_msrtype = IntelP6;
+                       break;
+               }                       
+       } else if (!strcmp(v.str, "AuthenticAMD") && (((ebx >> 4) & 0xF) == 6)) 
{
+               kdba_msrtype = AmdK6; 
+       }
+} 
+
+
 void
 kdba_installdbreg(kdb_bp_t *bp)
 {
@@ -708,6 +742,11 @@
 {
        u32  lv, hv;
 
+       /* Does the P5 have this? */ 
+       if (kdba_msrtype != IntelP6) { 
+               return;
+       }
+
        rdmsr(DEBUGCTLMSR, lv, hv);
        lv |= 0x1;      /* Set LBR enable */
        wrmsr(DEBUGCTLMSR, lv, hv);
@@ -734,6 +773,11 @@
        u32  bflv, bfhv;
        u32  btlv, bthv;
 
+       if (kdba_msrtype != IntelP6) { 
+               kdb_printf("Last branch information not supported on this 
CPU.\n");
+               return;
+       }
+
        rdmsr(LASTBRANCHFROMIP, bflv, bfhv);
        rdmsr(LASTBRANCHTOIP, btlv, bthv);
        kdb_printf("Last Branch IP, from: 0x%x  to 0x%x\n",
@@ -1087,6 +1131,7 @@
 void
 kdba_init(void)
 {
+       checkcpu(); 
        kdba_enablelbr();
 
        return;