| To: | "David S. Miller" <davem@xxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: Mystery packet killing tg3 |
| From: | "Michael Chan" <mchan@xxxxxxxxxxxx> |
| Date: | Tue, 03 May 2005 14:28:10 -0700 |
| Cc: | shemminger@xxxxxxxx, jgarzik@xxxxxxxxx, netdev@xxxxxxxxxxx |
| In-reply-to: | <20050503150333.1ac1c159.davem@xxxxxxxxxxxxx> |
| References: | <20050502162405.65dfb4a9@xxxxxxxxxxxxxxxxxxxxx> <20050502200251.38271b61.davem@xxxxxxxxxxxxx> <20050503140528.1bd2ac74@xxxxxxxxxxxxxxxxx> <20050503141314.441c9d75.davem@xxxxxxxxxxxxx> <1115152907.15156.26.camel@rh4> <20050503150333.1ac1c159.davem@xxxxxxxxxxxxx> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
On Tue, 2005-05-03 at 15:03 -0700, David S. Miller wrote: > Michael, there were no master/target abort bits set in the PCI status > register from his dump. If one of the DMA units locks up on the tg3, > will it still be able to update the PCI_STATUS register appropriately > when it encounters a DMA transaction error (ie. master or target abort) I believe so. Also, the DMA read and write status registers showed all zeros, meaning there were no DMA related errors: DEBUG: RDMAC_MODE[000003fc] RDMAC_STATUS[00000000] DEBUG: WDMAC_MODE[000003fc] WDMAC_STATUS[00000000] |
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