On Sun, 2005-02-20 at 11:46, Eugene Surovegin wrote:
> On Sat, Feb 19, 2005 at 09:27:31PM +0100, Andi Kleen wrote:
> > <speculating freely>
> > It would be nice if the NIC could asynchronously trigger prefetches in
> > the CPU. Currently a lot of the packet processing cost goes
> > to waiting for read cache misses.
> Just FYI :), Freescale 85xx TSECs can prefetch buffers into L2 cache.
> IIRC they call it buffer "stashing" and gianfar driver has a config
> option to enable such behavior.
> But in embedded world you usually don't see flashy PR releases for
> such features :).
yes ;-> Big bad Intel is now going to do this, the rest of the world
I have a modified sb1250 driver that i converted to NAPI that does this
(in kernel driver doesnt do either NAPI or stash packets into cache).
Reminds me i have to find that driver and submit.
In any case, the problem could be x86; about every MIPS board i have
seen (I heard PMC-sierra as well) can do this. To be fair to Big Bad
Intel, they may have made a PR or two ;->