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Re: Intel and TOE in the news

To: Eugene Surovegin <ebs@xxxxxxxxxxx>
Subject: Re: Intel and TOE in the news
From: jamal <hadi@xxxxxxxxxx>
Date: 21 Feb 2005 09:01:49 -0500
Cc: Andi Kleen <ak@xxxxxx>, "David S. Miller" <davem@xxxxxxxxxxxxx>, jgarzik@xxxxxxxxx, netdev@xxxxxxxxxxx
In-reply-to: <20050220164607.GA27891@xxxxxxxxxxxxxxxx>
Organization: jamalopolous
References: <4216B62D.6000502@xxxxxxxxx> <20050219041007.GA17896@xxxxxxxxxxxxxxxxx> <20050219114624.373af63f.davem@xxxxxxxxxxxxx> <m1psywb8i4.fsf@xxxxxx> <20050220164607.GA27891@xxxxxxxxxxxxxxxx>
Reply-to: hadi@xxxxxxxxxx
Sender: netdev-bounce@xxxxxxxxxxx
On Sun, 2005-02-20 at 11:46, Eugene Surovegin wrote:
> On Sat, Feb 19, 2005 at 09:27:31PM +0100, Andi Kleen wrote:
> > <speculating freely>
> > 
> > It would be nice if the NIC could asynchronously trigger prefetches in
> > the CPU. Currently a lot of the packet processing cost goes
> > to waiting for read cache misses.
> Just FYI :), Freescale 85xx TSECs can prefetch buffers into L2 cache. 
> IIRC they call it buffer "stashing" and gianfar driver has a config 
> option to enable such behavior.
> But in embedded world you usually don't see flashy PR releases for 
> such features :).

yes ;-> Big bad Intel is now going to do this, the rest of the world
better listen.
I have a modified sb1250 driver that i converted to NAPI that does this
(in kernel driver doesnt do either NAPI or stash packets into cache).
Reminds me i have to find that driver and submit. 
In any case, the problem could be x86; about every MIPS board i have
seen (I heard PMC-sierra as well) can do this. To be fair to Big Bad
Intel, they may have made a PR or two ;->


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