Re: Intel and TOE in the news

[Eugene Surovegin <ebs@xxxxxxxxxxx>]

On Sat, Feb 19, 2005 at 09:27:31PM +0100, Andi Kleen wrote:
> <speculating freely>
> 
> It would be nice if the NIC could asynchronously trigger prefetches in
> the CPU. Currently a lot of the packet processing cost goes
> to waiting for read cache misses.

Just FYI :), Freescale 85xx TSECs can prefetch buffers into L2 cache. 
IIRC they call it buffer "stashing" and gianfar driver has a config 
option to enable such behavior.

But in embedded world you usually don't see flashy PR releases for 
such features :).

--
Eugene.