"David S. Miller" wrote:
> Why were the NVRAM_ACCESS writes change to non-flushing
> register writes? Otherwise I think your patch is fine.
>
> Maybe it would be nice if you provided a detailed changelog
> of sorts, because other's might have similar questions like I
> did about why the tw32_f() --> tw32() changes were made.
>
>
>
>
No delay is required after writing that register to enable nvram access.
It was coded that way for A0 chips which required the flushing write
workaround to break fast back-to-back writes. A0 chips are not in
production so this workaround can be removed.
The new routines were written using the non-flushing write. To be
consistent, I changed some of the existing code to use non-flushing
write as well. However I wasn't very consistent when cutting and pasting
the code, so here is a new patch with more consistent use of the
non-flushing write.
Detailed changes:
- Add nvram size detection
- Add appropriate byte swapping to tg3_get_eeprom so that the same byte
stream is read in all systems
- Fix tg3_get_eeprom to read both eeprom and flash
- Add tg3_set_eeprom to write eeprom and flash
- Change tg3_nvram_init to detect all supported nvram devices
- Change tg3_nvram_read to properly detect Atmel flash that requires
address translation
- Increase nvram polling delay to account for slower eeprom devices
- Remove some of the flushing read that is not required for the
production 5750 devices
Signed-off-by: Michael Chan <mchan@xxxxxxxxxxxx>
tg3_nvram.patch1
Description: tg3_nvram.patch1
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