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Re: Asynchronous crypto layer.

To: Eugene Surovegin <ebs@xxxxxxxxxxx>
Subject: Re: Asynchronous crypto layer.
From: Evgeniy Polyakov <johnpol@xxxxxxxxxxx>
Date: Sun, 31 Oct 2004 01:04:15 +0400
Cc: hadi@xxxxxxxxxx, netdev@xxxxxxxxxxx, cryptoapi@xxxxxxxxxxxxxx
In-reply-to: <20041030203550.GB6256@xxxxxxxxxxxxxxxx>
Organization: MIPT
References: <1099030958.4944.148.camel@uganda> <1099053738.1024.104.camel@xxxxxxxxxxxxxxxx> <20041029180652.113f0f6e@xxxxxxxxxxxxxxxxxxxx> <20041030203550.GB6256@xxxxxxxxxxxxxxxx>
Reply-to: johnpol@xxxxxxxxxxx
Sender: netdev-bounce@xxxxxxxxxxx
On Sat, 30 Oct 2004 13:35:50 -0700
Eugene Surovegin <ebs@xxxxxxxxxxx> wrote:

> On Fri, Oct 29, 2004 at 06:06:52PM +0400, Evgeniy Polyakov wrote:
> > If we have a hardware accelerator chip, than we _already_ have improvements 
> > with even the worst async crypto layer, since software and hardware 
> > will work in parrallel.
> 
> This is not true. 
> 
> For example, if chip request setup and PCI transfer takes more than 
> just using sw implementation. This is reality for AES and short 
> packets.

You have dataflow of packets, if invoce expenses take less time
then you will win.
More than 1kbyte of data to be encrypted already beats time
need for software encryption on 266 mhz.
What hardware requires PCI transfer that will take more time
than it's encryption?
And what about asynchronous crypto? 
Kernel currently even can not generate RSA keys, although
necessity of such feature is under the question.

> 
> --
> Eugene


        Evgeniy Polyakov

Only failure makes us experts. -- Theo de Raadt

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