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[patch 3/9] use mmiowb in tg3_poll

To: davem@xxxxxxxxxx
Subject: [patch 3/9] use mmiowb in tg3_poll
From: akpm@xxxxxxxx
Date: Thu, 28 Oct 2004 00:19:41 -0700
Cc: jgarzik@xxxxxxxxx, netdev@xxxxxxxxxxx, akpm@xxxxxxxx, akepner@xxxxxxx
Sender: netdev-bounce@xxxxxxxxxxx
From: <akepner@xxxxxxx>

Returning from tg3_poll() without flushing the PIO write which reenables
interrupts can result in lower cpu utilization and higher throughput.  So
use a memory barrier, mmiowb(), instead of flushing the write with a PIO
read.

Signed-off-by: Arthur Kepner <akepner@xxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxx>
---

 25-akpm/drivers/net/tg3.c |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletion(-)

diff -puN drivers/net/tg3.c~use-mmiowb-in-tg3_poll drivers/net/tg3.c
--- 25/drivers/net/tg3.c~use-mmiowb-in-tg3_poll 2004-10-28 00:17:07.705632552 
-0700
+++ 25-akpm/drivers/net/tg3.c   2004-10-28 00:17:07.715631032 -0700
@@ -418,6 +418,20 @@ static void tg3_enable_ints(struct tg3 *
        tg3_cond_int(tp);
 }
 
+/* tg3_restart_ints
+ *  similar to tg3_enable_ints, but it can return without flushing the
+ *  PIO write which reenables interrupts
+ */
+static void tg3_restart_ints(struct tg3 *tp)
+{
+       tw32(TG3PCI_MISC_HOST_CTRL,
+               (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
+       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
+       mmiowb();
+
+       tg3_cond_int(tp);
+}
+
 static inline void tg3_netif_stop(struct tg3 *tp)
 {
        netif_poll_disable(tp->dev);
@@ -2789,7 +2803,7 @@ static int tg3_poll(struct net_device *n
        if (done) {
                spin_lock_irqsave(&tp->lock, flags);
                __netif_rx_complete(netdev);
-               tg3_enable_ints(tp);
+               tg3_restart_ints(tp);
                spin_unlock_irqrestore(&tp->lock, flags);
        }
 
_

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