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Re: The ultimate TOE design

To: Jeff Garzik <jgarzik@xxxxxxxxx>
Subject: Re: The ultimate TOE design
From: jamal <hadi@xxxxxxxxxx>
Date: 15 Sep 2004 20:57:59 -0400
Cc: "David S. Miller" <davem@xxxxxxxxxxxxx>, alan@xxxxxxxxxxxxxxxxxxx, paul@xxxxxxxx, netdev@xxxxxxxxxxx, leonid.grossman@xxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx
In-reply-to: <4148B2E5.50106@xxxxxxxxx>
Organization: jamalopolous
References: <4148991B.9050200@xxxxxxxxx> <Pine.LNX.4.61.0409152102050.23011@xxxxxxxxxxxxxxxxx> <1095275660.20569.0.camel@xxxxxxxxxxxxxxxxxxxxx> <4148A90F.80003@xxxxxxxxx> <20040915140123.14185ede.davem@xxxxxxxxxxxxx> <20040915210818.GA22649@xxxxxxxxxxxxx> <20040915141346.5c5e5377.davem@xxxxxxxxxxxxx> <4148B2E5.50106@xxxxxxxxx>
Reply-to: hadi@xxxxxxxxxx
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You are only allowed to start a TOE thread only every six months ;->

On a serious note, I think that PCI-express (if it lives upto its
expectation) will demolish dreams of a lot of these TOE investments.
Our problem is NOT the CPU right now (80% idle processing 450Kpps
forwarding). Bus and memory distance/latency are. If intel would get rid
of the big conspiracy in the form of chipset division and just integrate
the MC like AMD is, we'll be on our our way to kill TOE and a lot of the
network processors (like the IXP). Dang, running Linux is more exciting
than microcoding things to fit into a 2Kword program store. 

I rest my canadiana $.02 


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