| To: | <netdev@xxxxxxxxxxx> |
|---|---|
| Subject: | PCI fix for some platforms |
| From: | "Andriy Korud" <a.korud@xxxxxxxxxxxxx> |
| Date: | Wed, 30 Jun 2004 10:52:31 +0200 |
| Cc: | <prism54-private@xxxxxxxxxxx> |
| Sender: | netdev-bounce@xxxxxxxxxxx |
| Thread-index: | AcRef3tmILzf3BrFQWu3L2wWhTqA1g== |
| Thread-topic: | PCI fix for some platforms |
Hi, i've noticed that on some platforms (noticed on PPC/XScale embedded) PCI cacheline size is not initialized properly and therefore card uses slow "PCI read memory" command instead of optimal "PCI read memory line", which cause serious bendwidth limitations in case of 3+ cards on single PCI bus. Attached patch that fix this issue - please merge review. regards, -- Andriy Korud
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