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Re: [PATCH] fix BUG in tg3_tx

To: Greg Banks <gnb@xxxxxxx>
Subject: Re: [PATCH] fix BUG in tg3_tx
From: "David S. Miller" <davem@xxxxxxxxxx>
Date: Wed, 26 May 2004 11:01:21 -0700
Cc: mchan@xxxxxxxxxxxx, netdev@xxxxxxxxxxx
In-reply-to: <20040526160443.GD4557@sgi.com>
References: <B1508D50A0692F42B217C22C02D849727FEDB8@NT-IRVA-0741.brcm.ad.broadcom.com> <20040526160443.GD4557@sgi.com>
Sender: netdev-bounce@xxxxxxxxxxx
On Thu, 27 May 2004 02:04:43 +1000
Greg Banks <gnb@xxxxxxx> wrote:

> On a related note, is there a good reason why the tg3 driver uses
> the on-chip SRAM send ring by default instead of the host send ring?
> This seems like it would dramatically increase the PIO load on the
> chipset for some of the workloads I'm interested in.

Good question.

It actually results in better performance to use PIOs to the
chip to write the TXD descriptors.  You may be skeptical about
this but it cannot be denied that it does result in lower
latency as we don't have to wait for the chip to do it's next
prefetch and _furthermore_ this means that no CPU cache lines
will bounce from cpu-->device in order to get the descriptors
to the chip.

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