Re: [PATCH] r8169 NAPI addition

[Francois Romieu <romieu@xxxxxxxxxxxxx>]

Jon D Mason <jonmason@xxxxxxxxxx> :
[...]
> I assume you are referring to the driver being used in weakly ordered 
> memory model machines.  To address this I added a rmb() after the update 
> to the interrupt mask.

Nonono, it is a PCI thing. Writes to (pci-)MMIO registers are posted and
typically require a read in the MMIO range (or "some" time) to be committed
to the final device. (pci-)IO accesses do not exhibit this property.

--
Ueimor