Re: Route cache performance under stress

[Andi Kleen <ak@xxxxxxx>]

On Mon, Jun 09, 2003 at 03:03:34AM -0700, David S. Miller wrote:
>    From: Andi Kleen <ak@xxxxxxx>
>    Date: Mon, 9 Jun 2003 11:47:34 +0200
>    
>    gcc will generate a lot better code for the memsets if you can tell
>    it somehow they are long aligned and a multiple of 8 bytes.
> 
> True, but the real bug is that we're initializing any of this
> crap here at all.  Right now we write over the same cachelines
> 3 or so times.  It should really just happen once.

It's unlikely to be the reason for the profile hit on a modern x86.
They are all really fast at reading/writing L1. 

More likely it is the cache miss for fetching the lines initially.
Perhaps it is cache thrashing the dst_entry heads. Adding a strategic
prefetch somewhere early may help a lot.

-Andi