[Top] [All Lists]

Re: Route cache performance under stress

To: ak@xxxxxxx
Subject: Re: Route cache performance under stress
From: "David S. Miller" <davem@xxxxxxxxxx>
Date: Mon, 09 Jun 2003 03:03:34 -0700 (PDT)
Cc: sim@xxxxxxxxxxxxx, xerox@xxxxxxxxxx, fw@xxxxxxxxxxxxx, netdev@xxxxxxxxxxx, linux-net@xxxxxxxxxxxxxxx, kuznet@xxxxxxxxxxxxx, Robert.Olsson@xxxxxxxxxxx
In-reply-to: <20030609094734.GD2728@xxxxxxxxxxxxx>
References: <20030609081803.GF20613@xxxxxxxxxxxxx> <20030609.020116.10308258.davem@xxxxxxxxxx> <20030609094734.GD2728@xxxxxxxxxxxxx>
Sender: netdev-bounce@xxxxxxxxxxx
   From: Andi Kleen <ak@xxxxxxx>
   Date: Mon, 9 Jun 2003 11:47:34 +0200
   gcc will generate a lot better code for the memsets if you can tell
   it somehow they are long aligned and a multiple of 8 bytes.

True, but the real bug is that we're initializing any of this
crap here at all.  Right now we write over the same cachelines
3 or so times.  It should really just happen once.

<Prev in Thread] Current Thread [Next in Thread>