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Re: e1000 performance hack for ppc64 (Power4)

To: "Feldman, Scott" <scott.feldman@xxxxxxxxx>
Subject: Re: e1000 performance hack for ppc64 (Power4)
From: Anton Blanchard <anton@xxxxxxxxx>
Date: Sat, 14 Jun 2003 10:03:42 +1000
Cc: "David S. Miller" <davem@xxxxxxxxxx>, haveblue@xxxxxxxxxx, hdierks@xxxxxxxxxx, dwg@xxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, milliner@xxxxxxxxxx, ricardoz@xxxxxxxxxx, twichell@xxxxxxxxxx, netdev@xxxxxxxxxxx
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> I thought the answer was no, so I double checked with a couple of
> hardware guys, and the answer is still no.

Hi Scott,

Thats a pity, the e100 docs on sourceforge show it can do what we want,
it would be nice if e1000 had this feature too :)

4.2.2 Read Align

The Read Align feature is aimed to enhance performance in cache line
oriented systems. Starting a PCI transaction in these systems on a
non-cache line aligned address may result in low  performance. To solve
this performance problem, the controller can be configured to terminate
Transmit DMA cycles on a cache line boundary, and start the next
transaction on a cache line aligned address. This  feature is enabled
when the Read Align Enable bit is set in device Configure command
(Section 6.4.2.3, "Configure (010b)").

If this bit is set, the device operates as follows:

* When the device is close to running out of resources on the Transmit
* DMA (in other words, the Transmit FIFO is almost full), it attempts to
* terminate the read transaction on the nearest cache line boundary when 
* possible.

* When the arbitration counters feature is enabled (maximum Transmit DMA
* byte count value is set in configuration space), the device switches
* to other pending DMAs on cache line boundary only.

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